Commit 1940c25e authored by Abel Vesa's avatar Abel Vesa Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: x1e80100: Add display nodes 



Add the required nodes to support display on X1E80100.

Co-developed-by: default avatarSibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: default avatarSibi Sankar <quic_sibis@quicinc.com>
Co-developed-by: default avatarRajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: default avatarRajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-8-2c0e691cfa3b@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 5eb83fc1

arch/arm64/boot/dts/qcom/x1e80100.dtsi

+519 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 */



#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>

#include <dt-bindings/clock/qcom,x1e80100-gcc.h>

#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>

#include <dt-bindings/dma/qcom-gpi.h>
@@ -3352,6 +3353,524 @@ usb_1_ss1_role_switch: endpoint { 
			};

		};



		mdss: display-subsystem@ae00000 {

			compatible = "qcom,x1e80100-mdss";

			reg = <0 0x0ae00000 0 0x1000>;

			reg-names = "mdss";



			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

				 <&gcc GCC_DISP_HF_AXI_CLK>,

				 <&dispcc DISP_CC_MDSS_MDP_CLK>;



			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;



			interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS

					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,

					<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS

					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,

					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY

					 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;

			interconnect-names = "mdp0-mem",

					     "mdp1-mem",

					     "cpu-cfg";



			power-domains = <&dispcc MDSS_GDSC>;



			iommus = <&apps_smmu 0x1c00 0x2>;



			interrupt-controller;

			#interrupt-cells = <1>;



			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			status = "disabled";



			mdss_mdp: display-controller@ae01000 {

				compatible = "qcom,x1e80100-dpu";

				reg = <0 0x0ae01000 0 0x8f000>,

				      <0 0x0aeb0000 0 0x2008>;

				reg-names = "mdp",

					    "vbif";



				interrupts-extended = <&mdss 0>;



				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

					 <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

					 <&dispcc DISP_CC_MDSS_MDP_CLK>,

					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

				clock-names = "nrt_bus",

					      "iface",

					      "lut",

					      "core",

					      "vsync";



				operating-points-v2 = <&mdp_opp_table>;



				power-domains = <&rpmhpd RPMHPD_MMCX>;



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						mdss_intf0_out: endpoint {

							remote-endpoint = <&mdss_dp0_in>;

						};

					};



					port@4 {

						reg = <4>;



						mdss_intf4_out: endpoint {

							remote-endpoint = <&mdss_dp1_in>;

						};

					};



					port@5 {

						reg = <5>;



						mdss_intf5_out: endpoint {

							remote-endpoint = <&mdss_dp3_in>;

						};

					};



					port@6 {

						reg = <6>;



						mdss_intf6_out: endpoint {

							remote-endpoint = <&mdss_dp2_in>;

						};

					};

				};



				mdp_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-200000000 {

						opp-hz = /bits/ 64 <200000000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-325000000 {

						opp-hz = /bits/ 64 <325000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-375000000 {

						opp-hz = /bits/ 64 <375000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};



					opp-514000000 {

						opp-hz = /bits/ 64 <514000000>;

						required-opps = <&rpmhpd_opp_nom>;

					};



					opp-575000000 {

						opp-hz = /bits/ 64 <575000000>;

						required-opps = <&rpmhpd_opp_nom_l1>;

					};

				};

			};



			mdss_dp0: displayport-controller@ae90000 {

				compatible = "qcom,x1e80100-dp";

				reg = <0 0xae90000 0 0x200>,

				      <0 0xae90200 0 0x200>,

				      <0 0xae90400 0 0x600>,

				      <0 0xae91000 0 0x400>,

				      <0 0xae91400 0 0x400>;



				interrupts-extended = <&mdss 12>;



				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;

				clock-names = "core_iface",

					      "core_aux",

					      "ctrl_link",

					      "ctrl_link_iface",

					      "stream_pixel";



				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,

						  <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;

				assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,

							 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;



				operating-points-v2 = <&mdss_dp0_opp_table>;



				power-domains = <&rpmhpd RPMHPD_MMCX>;



				phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;

				phy-names = "dp";



				#sound-dai-cells = <0>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						mdss_dp0_in: endpoint {

							remote-endpoint = <&mdss_intf0_out>;

						};

					};



					port@1 {

						reg = <1>;



						mdss_dp0_out: endpoint {

						};

					};

				};



				mdss_dp0_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-160000000 {

						opp-hz = /bits/ 64 <160000000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-270000000 {

						opp-hz = /bits/ 64 <270000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-540000000 {

						opp-hz = /bits/ 64 <540000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};



					opp-810000000 {

						opp-hz = /bits/ 64 <810000000>;

						required-opps = <&rpmhpd_opp_nom>;

					};

				};

			};



			mdss_dp1: displayport-controller@ae98000 {

				compatible = "qcom,x1e80100-dp";

				reg = <0 0xae98000 0 0x200>,

				      <0 0xae98200 0 0x200>,

				      <0 0xae98400 0 0x600>,

				      <0 0xae99000 0 0x400>,

				      <0 0xae99400 0 0x400>;



				interrupts-extended = <&mdss 13>;



				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;

				clock-names = "core_iface",

					      "core_aux",

					      "ctrl_link",

					      "ctrl_link_iface",

					      "stream_pixel";



				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,

						  <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;

				assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,

							 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;



				operating-points-v2 = <&mdss_dp1_opp_table>;



				power-domains = <&rpmhpd RPMHPD_MMCX>;



				phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>;

				phy-names = "dp";



				#sound-dai-cells = <0>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						mdss_dp1_in: endpoint {

							remote-endpoint = <&mdss_intf4_out>;

						};

					};



					port@1 {

						reg = <1>;



						mdss_dp1_out: endpoint {

						};

					};

				};



				mdss_dp1_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-160000000 {

						opp-hz = /bits/ 64 <160000000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-270000000 {

						opp-hz = /bits/ 64 <270000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-540000000 {

						opp-hz = /bits/ 64 <540000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};



					opp-810000000 {

						opp-hz = /bits/ 64 <810000000>;

						required-opps = <&rpmhpd_opp_nom>;

					};

				};

			};



			mdss_dp2: displayport-controller@ae9a000 {

				compatible = "qcom,x1e80100-dp";

				reg = <0 0xae9a000 0 0x200>,

				      <0 0xae9a200 0 0x200>,

				      <0 0xae9a400 0 0x600>,

				      <0 0xae9b000 0 0x400>,

				      <0 0xae9b400 0 0x400>;



				interrupts-extended = <&mdss 14>;



				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;

				clock-names = "core_iface",

					      "core_aux",

					      "ctrl_link",

					      "ctrl_link_iface",

					      "stream_pixel";



				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,

						  <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;

				assigned-clock-parents = <&mdss_dp2_phy 0>,

							 <&mdss_dp2_phy 1>;



				operating-points-v2 = <&mdss_dp2_opp_table>;



				power-domains = <&rpmhpd RPMHPD_MMCX>;



				phys = <&mdss_dp2_phy>;

				phy-names = "dp";



				#sound-dai-cells = <0>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						mdss_dp2_in: endpoint {

							remote-endpoint = <&mdss_intf6_out>;

						};

					};



					port@1 {

						reg = <1>;

					};

				};



				mdss_dp2_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-160000000 {

						opp-hz = /bits/ 64 <160000000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-270000000 {

						opp-hz = /bits/ 64 <270000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-540000000 {

						opp-hz = /bits/ 64 <540000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};



					opp-810000000 {

						opp-hz = /bits/ 64 <810000000>;

						required-opps = <&rpmhpd_opp_nom>;

					};

				};

			};



			mdss_dp3: displayport-controller@aea0000 {

				compatible = "qcom,x1e80100-dp";

				reg = <0 0xaea0000 0 0x200>,

				      <0 0xaea0200 0 0x200>,

				      <0 0xaea0400 0 0x600>,

				      <0 0xaea1000 0 0x400>,

				      <0 0xaea1400 0 0x400>;



				interrupts-extended = <&mdss 15>;



				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,

					 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;

				clock-names = "core_iface",

					      "core_aux",

					      "ctrl_link",

					      "ctrl_link_iface",

					      "stream_pixel";



				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,

						  <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;

				assigned-clock-parents = <&mdss_dp3_phy 0>,

							 <&mdss_dp3_phy 1>;



				operating-points-v2 = <&mdss_dp3_opp_table>;



				power-domains = <&rpmhpd RPMHPD_MMCX>;



				phys = <&mdss_dp3_phy>;

				phy-names = "dp";



				#sound-dai-cells = <0>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						mdss_dp3_in: endpoint {

							remote-endpoint = <&mdss_intf5_out>;



							link-frequencies = /bits/ 64 <8100000000>;

						};

					};



					port@1 {

						reg = <1>;

					};

				};



				mdss_dp3_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-160000000 {

						opp-hz = /bits/ 64 <160000000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-270000000 {

						opp-hz = /bits/ 64 <270000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-540000000 {

						opp-hz = /bits/ 64 <540000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};



					opp-810000000 {

						opp-hz = /bits/ 64 <810000000>;

						required-opps = <&rpmhpd_opp_nom>;

					};

				};

			};



		};



		mdss_dp2_phy: phy@aec2a00 {

			compatible = "qcom,x1e80100-dp-phy";

			reg = <0 0x0aec2a00 0 0x19c>,

			      <0 0x0aec2200 0 0xec>,

			      <0 0x0aec2600 0 0xec>,

			      <0 0x0aec2000 0 0x1c8>;



			clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,

				 <&dispcc DISP_CC_MDSS_AHB_CLK>;

			clock-names = "aux",

				      "cfg_ahb";



			power-domains = <&rpmhpd RPMHPD_MX>;



			#clock-cells = <1>;

			#phy-cells = <0>;



			status = "disabled";

		};



		mdss_dp3_phy: phy@aec5a00 {

			compatible = "qcom,x1e80100-dp-phy";

			reg = <0 0x0aec5a00 0 0x19c>,

			      <0 0x0aec5200 0 0xec>,

			      <0 0x0aec5600 0 0xec>,

			      <0 0x0aec5000 0 0x1c8>;



			clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,

				 <&dispcc DISP_CC_MDSS_AHB_CLK>;

			clock-names = "aux",

				      "cfg_ahb";



			power-domains = <&rpmhpd RPMHPD_MX>;



			#clock-cells = <1>;

			#phy-cells = <0>;



			status = "disabled";

		};



		dispcc: clock-controller@af00000 {

			compatible = "qcom,x1e80100-dispcc";

			reg = <0 0x0af00000 0 0x20000>;

			clocks = <&bi_tcxo_div2>,

				 <&bi_tcxo_ao_div2>,

				 <&gcc GCC_DISP_AHB_CLK>,

				 <&sleep_clk>,

				 <0>, /* dsi0 */

				 <0>,

				 <0>, /* dsi1 */

				 <0>,

				 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */

				 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,

				 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */

				 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,

				 <&mdss_dp2_phy 0>, /* dp2 */

				 <&mdss_dp2_phy 1>,

				 <&mdss_dp3_phy 0>, /* dp3 */

				 <&mdss_dp3_phy 1>;

			power-domains = <&rpmhpd RPMHPD_MMCX>;

			required-opps = <&rpmhpd_opp_low_svs>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,x1e80100-pdc", "qcom,pdc";

			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;