Commit 1c6285e1 authored by Pierre-Hugues Husson's avatar Pierre-Hugues Husson Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: msm8998: add venus node 



Now that the venus clocks are fixed, we can add the DT node.

Signed-off-by: default avatarPierre-Hugues Husson <phhusson@freebox.fr>
Signed-off-by: default avatarMarc Gonzalez <mgonzalez@freebox.fr>
Reviewed-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: default avatarVikash Garodia <quic_vgarodia@quicinc.com>
Link: https://lore.kernel.org/r/6d86a6a3-4d99-4fda-9a38-7688587237e6@freebox.fr


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 818c2676

arch/arm64/boot/dts/qcom/msm8998.dtsi

+48 −0
Original line number Diff line number Diff line
@@ -3000,6 +3000,54 @@ mdss_dsi1_phy: phy@c996400 { 
			};

		};



		venus: video-codec@cc00000 {

			compatible = "qcom,msm8998-venus";

			reg = <0x0cc00000 0xff000>;

			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;

			power-domains = <&mmcc VIDEO_TOP_GDSC>;

			clocks = <&mmcc VIDEO_CORE_CLK>,

				 <&mmcc VIDEO_AHB_CLK>,

				 <&mmcc VIDEO_AXI_CLK>,

				 <&mmcc VIDEO_MAXI_CLK>;

			clock-names = "core", "iface", "bus", "mbus";

			iommus = <&mmss_smmu 0x400>,

				 <&mmss_smmu 0x401>,

				 <&mmss_smmu 0x40a>,

				 <&mmss_smmu 0x407>,

				 <&mmss_smmu 0x40e>,

				 <&mmss_smmu 0x40f>,

				 <&mmss_smmu 0x408>,

				 <&mmss_smmu 0x409>,

				 <&mmss_smmu 0x40b>,

				 <&mmss_smmu 0x40c>,

				 <&mmss_smmu 0x40d>,

				 <&mmss_smmu 0x410>,

				 <&mmss_smmu 0x421>,

				 <&mmss_smmu 0x428>,

				 <&mmss_smmu 0x429>,

				 <&mmss_smmu 0x42b>,

				 <&mmss_smmu 0x42c>,

				 <&mmss_smmu 0x42d>,

				 <&mmss_smmu 0x411>,

				 <&mmss_smmu 0x431>;

			memory-region = <&venus_mem>;

			status = "disabled";



			video-decoder {

				compatible = "venus-decoder";

				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;

				clock-names = "core";

				power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>;

			};



			video-encoder {

				compatible = "venus-encoder";

				clocks = <&mmcc VIDEO_SUBCORE1_CLK>;

				clock-names = "core";

				power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>;

			};

		};



		mmss_smmu: iommu@cd00000 {

			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";

			reg = <0x0cd00000 0x40000>;