Unverified Commit 1e748354 authored by Andy Chiu's avatar Andy Chiu Committed by Palmer Dabbelt
Browse files

riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection 



Multiple Vector subextensions are added. Also, the patch takes care of
the dependencies of Vector subextensions by macro expansions. So, if
some "embedded" platform only reports "zve64f" on the ISA string, the
parser is able to expand it to zve32x zve32f zve64x and zve64f.

Signed-off-by: default avatarAndy Chiu <andy.chiu@sifive.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240510-zve-detection-v5-5-0711bdd26c12@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 037df296

arch/riscv/include/asm/hwcap.h

+5 −0
Original line number Diff line number Diff line
@@ -81,6 +81,11 @@ 
#define RISCV_ISA_EXT_ZTSO		72

#define RISCV_ISA_EXT_ZACAS		73

#define RISCV_ISA_EXT_XANDESPMU		74

#define RISCV_ISA_EXT_ZVE32X		75

#define RISCV_ISA_EXT_ZVE32F		76

#define RISCV_ISA_EXT_ZVE64X		77

#define RISCV_ISA_EXT_ZVE64F		78

#define RISCV_ISA_EXT_ZVE64D		79



#define RISCV_ISA_EXT_XLINUXENVCFG	127

arch/riscv/kernel/cpufeature.c

+40 −1
Original line number Diff line number Diff line
@@ -188,6 +188,40 @@ static const unsigned int riscv_zvbb_exts[] = { 
	RISCV_ISA_EXT_ZVKB

};



#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST	\

	RISCV_ISA_EXT_ZVE64X,		\

	RISCV_ISA_EXT_ZVE32F,		\

	RISCV_ISA_EXT_ZVE32X



#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST	\

	RISCV_ISA_EXT_ZVE64F,		\

	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST



#define RISCV_ISA_EXT_V_IMPLY_LIST	\

	RISCV_ISA_EXT_ZVE64D,		\

	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST



static const unsigned int riscv_zve32f_exts[] = {

	RISCV_ISA_EXT_ZVE32X

};



static const unsigned int riscv_zve64f_exts[] = {

	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST

};



static const unsigned int riscv_zve64d_exts[] = {

	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST

};



static const unsigned int riscv_v_exts[] = {

	RISCV_ISA_EXT_V_IMPLY_LIST

};



static const unsigned int riscv_zve64x_exts[] = {

	RISCV_ISA_EXT_ZVE32X,

	RISCV_ISA_EXT_ZVE64X

};



/*

 * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V

 * privileged ISA, the existence of the CSRs is implied by any extension which
@@ -245,7 +279,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { 
	__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),

	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),

	__RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),

	__RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),

	__RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),

	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),

	__RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts),

	__RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts),
@@ -280,6 +314,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { 
	__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),

	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),

	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),

	__RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),

	__RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),

	__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),

	__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),

	__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),

	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),

	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),

	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),