dt-bindings: fpga: altera: Convert bridge bindings to yaml

Altera FPGA To SDRAM Bridge Driver

Required properties:

- compatible		: Should contain "altr,socfpga-fpga2sdram-bridge"

See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.

Example:

	fpga_bridge3: fpga-bridge@ffc25080 {

		compatible = "altr,socfpga-fpga2sdram-bridge";

		reg = <0xffc25080 0x4>;

		bridge-enable = <0>;

	};

Altera Freeze Bridge Controller Driver

The Altera Freeze Bridge Controller manages one or more freeze bridges.

The controller can freeze/disable the bridges which prevents signal

changes from passing through the bridge.  The controller can also

unfreeze/enable the bridges which allows traffic to pass through the

bridge normally.

Required properties:

- compatible		: Should contain "altr,freeze-bridge-controller"

- regs			: base address and size for freeze bridge module

See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.

Example:

	freeze-controller@100000450 {

		compatible = "altr,freeze-bridge-controller";

		regs = <0x1000 0x10>;

		bridge-enable = <0>;

	};

Altera FPGA/HPS Bridge Driver

Required properties:

- regs		: base address and size for AXI bridge module

- compatible	: Should contain one of:

		  "altr,socfpga-lwhps2fpga-bridge",

		  "altr,socfpga-hps2fpga-bridge", or

		  "altr,socfpga-fpga2hps-bridge"

- resets	: Phandle and reset specifier for this bridge's reset

- clocks	: Clocks used by this module.

See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.

Example:

	fpga_bridge0: fpga-bridge@ff400000 {

		compatible = "altr,socfpga-lwhps2fpga-bridge";

		reg = <0xff400000 0x100000>;

		resets = <&rst LWHPS2FPGA_RESET>;

		clocks = <&l4_main_clk>;

		bridge-enable = <0>;

	};

	fpga_bridge1: fpga-bridge@ff500000 {

		compatible = "altr,socfpga-hps2fpga-bridge";

		reg = <0xff500000 0x10000>;

		resets = <&rst HPS2FPGA_RESET>;

		clocks = <&l4_main_clk>;

		bridge-enable = <1>;

	};

	fpga_bridge2: fpga-bridge@ff600000 {

		compatible = "altr,socfpga-fpga2hps-bridge";

		reg = <0xff600000 0x100000>;

		resets = <&rst FPGA2HPS_RESET>;

		clocks = <&l4_main_clk>;

	};

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Altera Freeze Bridge Controller

description:

  The Altera Freeze Bridge Controller manages one or more freeze bridges.

  The controller can freeze/disable the bridges which prevents signal

  changes from passing through the bridge. The controller can also

  unfreeze/enable the bridges which allows traffic to pass through the bridge

  normally.

maintainers:

  - Xu Yilun <yilun.xu@intel.com>

allOf:

  - $ref: fpga-bridge.yaml#

properties:

  compatible:

    const: altr,freeze-bridge-controller

  reg:

    maxItems: 1

required:

  - compatible

  - reg

unevaluatedProperties: false

examples:

  - |

    fpga-bridge@100000450 {

        compatible = "altr,freeze-bridge-controller";

        reg = <0x1000 0x10>;

        bridge-enable = <0>;

    };

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/fpga/altr,socfpga-fpga2sdram-bridge.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Altera FPGA To SDRAM Bridge

maintainers:

  - Xu Yilun <yilun.xu@intel.com>

allOf:

  - $ref: fpga-bridge.yaml#

properties:

  compatible:

    const: altr,socfpga-fpga2sdram-bridge

  reg:

    maxItems: 1

required:

  - compatible

unevaluatedProperties: false

examples:

  - |

    fpga-bridge@ffc25080 {

        compatible = "altr,socfpga-fpga2sdram-bridge";

        reg = <0xffc25080 0x4>;

        bridge-enable = <0>;

    };