Commit 23eca34e authored by Jesse Brandeburg's avatar Jesse Brandeburg Committed by Tony Nguyen
Browse files

ice: field prep conversion 



Refactor ice driver to use FIELD_PREP(), which reduces lines of code
and adds clarity of intent.

This code was generated by the following coccinelle/spatch script and
then manually repaired.

Several places I changed to OR into a single variable with |= instead of
using a multi-line statement with trailing OR operators, as it
(subjectively) makes the code clearer.

A local variable vmvf_and_timeout was created and used to avoid multiple
logical ORs being __le16 converted, which shortened some lines and makes
the code cleaner.

Also clean up a couple of places where conversions were made to have the
code read more clearly/consistently.

@prep2@
constant shift,mask;
type T;
expression a;
@@
-(((T)(a) << shift) & mask)
+FIELD_PREP(mask, a)

@prep@
constant shift,mask;
type T;
expression a;
@@
-((T)((a) << shift) & mask)
+FIELD_PREP(mask, a)

Cc: Julia Lawall <Julia.Lawall@inria.fr>
CC: Alexander Lobakin <aleksander.lobakin@intel.com>
Reviewed-by: default avatarMarcin Szycik <marcin.szycik@linux.intel.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Signed-off-by: default avatarJesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent 9b7f1804

drivers/net/ethernet/intel/ice/ice_base.c

+8 −12
Original line number Diff line number Diff line
@@ -242,14 +242,10 @@ static void ice_cfg_itr_gran(struct ice_hw *hw) 
	      GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US))

		return;



	regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) &

		  GLINT_CTL_ITR_GRAN_200_M) |

		 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) &

		  GLINT_CTL_ITR_GRAN_100_M) |

		 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) &

		  GLINT_CTL_ITR_GRAN_50_M) |

		 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) &

		  GLINT_CTL_ITR_GRAN_25_M);

	regval = FIELD_PREP(GLINT_CTL_ITR_GRAN_200_M, ICE_ITR_GRAN_US) |

		 FIELD_PREP(GLINT_CTL_ITR_GRAN_100_M, ICE_ITR_GRAN_US) |

		 FIELD_PREP(GLINT_CTL_ITR_GRAN_50_M, ICE_ITR_GRAN_US) |

		 FIELD_PREP(GLINT_CTL_ITR_GRAN_25_M, ICE_ITR_GRAN_US);

	wr32(hw, GLINT_CTL, regval);

}
@@ -921,10 +917,10 @@ ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx) 
	struct ice_hw *hw = &pf->hw;

	u32 val;



	itr_idx = (itr_idx << QINT_TQCTL_ITR_INDX_S) & QINT_TQCTL_ITR_INDX_M;

	itr_idx = FIELD_PREP(QINT_TQCTL_ITR_INDX_M, itr_idx);



	val = QINT_TQCTL_CAUSE_ENA_M | itr_idx |

	      ((msix_idx << QINT_TQCTL_MSIX_INDX_S) & QINT_TQCTL_MSIX_INDX_M);

	      FIELD_PREP(QINT_TQCTL_MSIX_INDX_M, msix_idx);



	wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);

	if (ice_is_xdp_ena_vsi(vsi)) {
@@ -953,10 +949,10 @@ ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx) 
	struct ice_hw *hw = &pf->hw;

	u32 val;



	itr_idx = (itr_idx << QINT_RQCTL_ITR_INDX_S) & QINT_RQCTL_ITR_INDX_M;

	itr_idx = FIELD_PREP(QINT_RQCTL_ITR_INDX_M, itr_idx);



	val = QINT_RQCTL_CAUSE_ENA_M | itr_idx |

	      ((msix_idx << QINT_RQCTL_MSIX_INDX_S) & QINT_RQCTL_MSIX_INDX_M);

	      FIELD_PREP(QINT_RQCTL_MSIX_INDX_M, msix_idx);



	wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);

drivers/net/ethernet/intel/ice/ice_common.c

+16 −19
Original line number Diff line number Diff line
@@ -3884,6 +3884,7 @@ ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 
{

	struct ice_aqc_sff_eeprom *cmd;

	struct ice_aq_desc desc;

	u16 i2c_bus_addr;

	int status;



	if (!data || (mem_addr & 0xff00))
@@ -3894,15 +3895,13 @@ ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 
	desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD);

	cmd->lport_num = (u8)(lport & 0xff);

	cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);

	cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) &

					 ICE_AQC_SFF_I2CBUS_7BIT_M) |

					((set_page <<

					  ICE_AQC_SFF_SET_EEPROM_PAGE_S) &

					 ICE_AQC_SFF_SET_EEPROM_PAGE_M));

	cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff);

	cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);

	i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) |

		       FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page);

	if (write)

		cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE);

		i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE;

	cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr);

	cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff);

	cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M);



	status = ice_aq_send_cmd(hw, &desc, data, length, cd);

	return status;
@@ -4157,6 +4156,7 @@ ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 
	struct ice_aqc_dis_txq_item *item;

	struct ice_aqc_dis_txqs *cmd;

	struct ice_aq_desc desc;

	u16 vmvf_and_timeout;

	u16 i, sz = 0;

	int status;
@@ -4172,27 +4172,26 @@ ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 


	cmd->num_entries = num_qgrps;



	cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &

					    ICE_AQC_Q_DIS_TIMEOUT_M);

	vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5);



	switch (rst_src) {

	case ICE_VM_RESET:

		cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;

		cmd->vmvf_and_timeout |=

			cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);

		vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M;

		break;

	case ICE_VF_RESET:

		cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;

		/* In this case, FW expects vmvf_num to be absolute VF ID */

		cmd->vmvf_and_timeout |=

			cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) &

				    ICE_AQC_Q_DIS_VMVF_NUM_M);

		vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) &

				    ICE_AQC_Q_DIS_VMVF_NUM_M;

		break;

	case ICE_NO_RESET:

	default:

		break;

	}



	cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout);



	/* flush pipe on time out */

	cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;

	/* If no queue group info, we are in a reset flow. Issue the AQ */
@@ -4267,10 +4266,8 @@ ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 
	cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG;

	cmd->num_qs = num_qs;

	cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M);

	cmd->port_num_chng |= (newport << ICE_AQC_Q_CFG_DST_PRT_S) &

			      ICE_AQC_Q_CFG_DST_PRT_M;

	cmd->time_out = (5 << ICE_AQC_Q_CFG_TIMEOUT_S) &

			ICE_AQC_Q_CFG_TIMEOUT_M;

	cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport);

	cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5);

	cmd->blocked_cgds = 0;



	status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);

drivers/net/ethernet/intel/ice/ice_dcb.c

+1 −2
Original line number Diff line number Diff line
@@ -35,8 +35,7 @@ ice_aq_get_lldp_mib(struct ice_hw *hw, u8 bridge_type, u8 mib_type, void *buf, 
	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_get_mib);



	cmd->type = mib_type & ICE_AQ_LLDP_MIB_TYPE_M;

	cmd->type |= (bridge_type << ICE_AQ_LLDP_BRID_TYPE_S) &

		ICE_AQ_LLDP_BRID_TYPE_M;

	cmd->type |= FIELD_PREP(ICE_AQ_LLDP_BRID_TYPE_M, bridge_type);



	desc.datalen = cpu_to_le16(buf_size);

drivers/net/ethernet/intel/ice/ice_dcb_lib.c

+1 −1
Original line number Diff line number Diff line
@@ -934,7 +934,7 @@ ice_tx_prepare_vlan_flags_dcb(struct ice_tx_ring *tx_ring, 
	    skb->priority != TC_PRIO_CONTROL) {

		first->vid &= ~VLAN_PRIO_MASK;

		/* Mask the lower 3 bits to set the 802.1p priority */

		first->vid |= (skb->priority << VLAN_PRIO_SHIFT) & VLAN_PRIO_MASK;

		first->vid |= FIELD_PREP(VLAN_PRIO_MASK, skb->priority);

		/* if this is not already set it means a VLAN 0 + priority needs

		 * to be offloaded

		 */

drivers/net/ethernet/intel/ice/ice_eswitch.c

+2 −2
Original line number Diff line number Diff line
@@ -358,8 +358,8 @@ ice_eswitch_set_target_vsi(struct sk_buff *skb, 
		off->cd_qw1 |= (cd_cmd | ICE_TX_DESC_DTYPE_CTX);

	} else {

		cd_cmd = ICE_TX_CTX_DESC_SWTCH_VSI << ICE_TXD_CTX_QW1_CMD_S;

		dst_vsi = ((u64)dst->u.port_info.port_id <<

			   ICE_TXD_CTX_QW1_VSI_S) & ICE_TXD_CTX_QW1_VSI_M;

		dst_vsi = FIELD_PREP(ICE_TXD_CTX_QW1_VSI_M,

				     dst->u.port_info.port_id);

		off->cd_qw1 = cd_cmd | dst_vsi | ICE_TX_DESC_DTYPE_CTX;

	}

}