dt-bindings: interrupt-controller: Convert marvell,cp110-icu to DT schema

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/marvell,cp110-icu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

maintainers:

  - Miquel Raynal <miquel.raynal@bootlin.com>

  - Thomas Petazzoni <thomas.petazzoni@bootlin.com>

title: Marvell ICU Interrupt Controller

description:

  The Marvell ICU (Interrupt Consolidation Unit) controller is responsible for

  collecting all wired-interrupt sources in the CP and communicating them to the

  GIC in the AP. The unit translates interrupt requests on input wires to MSG

  memory mapped transactions to the GIC. These messages access different GIC

  memory areas depending on their type (NSR, SR, SEI, REI, etc).

properties:

  compatible:

    const: marvell,cp110-icu

  reg:

    maxItems: 1

  '#address-cells':

    const: 1

  '#size-cells':

    const: 1

  ranges: true

patternProperties:

  "^interrupt-controller@":

    type: object

    description: Interrupt group child nodes

    additionalProperties: false

    properties:

      compatible:

        enum:

          - marvell,cp110-icu-nsr

          - marvell,cp110-icu-sr

          - marvell,cp110-icu-sei

          - marvell,cp110-icu-rei

      reg:

        maxItems: 1

      '#interrupt-cells':

        const: 2

      interrupt-controller: true

      msi-parent:

        maxItems: 1

        description: Phandle to the GICP controller

    required:

      - compatible

      - reg

      - '#interrupt-cells'

      - interrupt-controller

      - msi-parent

required:

  - compatible

  - reg

additionalProperties: false

examples:

  - |

    interrupt-controller@1e0000 {

        compatible = "marvell,cp110-icu";

        reg = <0x1e0000 0x440>;

        #address-cells = <1>;

        #size-cells = <1>;

        ranges;

        interrupt-controller@10 {

                compatible = "marvell,cp110-icu-nsr";

                reg = <0x10 0x20>;

                #interrupt-cells = <2>;

                interrupt-controller;

                msi-parent = <&gicp>;

        };

        interrupt-controller@50 {

                compatible = "marvell,cp110-icu-sei";

                reg = <0x50 0x10>;

                #interrupt-cells = <2>;

                interrupt-controller;

                msi-parent = <&sei>;

        };

    };

Marvell ICU Interrupt Controller

--------------------------------

The Marvell ICU (Interrupt Consolidation Unit) controller is

responsible for collecting all wired-interrupt sources in the CP and

communicating them to the GIC in the AP, the unit translates interrupt

requests on input wires to MSG memory mapped transactions to the GIC.

These messages will access a different GIC memory area depending on

their type (NSR, SR, SEI, REI, etc).

Required properties:

- compatible: Should be "marvell,cp110-icu"

- reg: Should contain ICU registers location and length.

Subnodes: Each group of interrupt is declared as a subnode of the ICU,

with their own compatible.

Required properties for the icu_nsr/icu_sei subnodes:

- compatible: Should be one of:

              * "marvell,cp110-icu-nsr"

	      * "marvell,cp110-icu-sr"

	      * "marvell,cp110-icu-sei"

	      * "marvell,cp110-icu-rei"

- #interrupt-cells: Specifies the number of cells needed to encode an

  interrupt source. The value shall be 2.

  The 1st cell is the index of the interrupt in the ICU unit.

  The 2nd cell is the type of the interrupt. See arm,gic.txt for

  details.

- interrupt-controller: Identifies the node as an interrupt

  controller.

- msi-parent: Should point to the GICP controller, the GIC extension

  that allows to trigger interrupts using MSG memory mapped

  transactions.

Note: each 'interrupts' property referring to any 'icu_xxx' node shall

      have a different number within [0:206].

Example:

icu: interrupt-controller@1e0000 {

	compatible = "marvell,cp110-icu";

	reg = <0x1e0000 0x440>;

	CP110_LABEL(icu_nsr): interrupt-controller@10 {

		compatible = "marvell,cp110-icu-nsr";

		reg = <0x10 0x20>;

		#interrupt-cells = <2>;

		interrupt-controller;

		msi-parent = <&gicp>;

	};

	CP110_LABEL(icu_sei): interrupt-controller@50 {

		compatible = "marvell,cp110-icu-sei";

		reg = <0x50 0x10>;

		#interrupt-cells = <2>;

		interrupt-controller;

		msi-parent = <&sei>;

	};

};

node1 {

	interrupt-parent = <&icu_nsr>;

	interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;

};

node2 {

	interrupt-parent = <&icu_sei>;

	interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;

};

/* Would not work with the above nodes */

node3 {

	interrupt-parent = <&icu_nsr>;

	interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;

};

The legacy bindings were different in this way:

- #interrupt-cells: The value was 3.

	The 1st cell was the group type of the ICU interrupt. Possible

	group types were:

	ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure

	ICU_GRP_SR  (0x1) : Shared peripheral interrupt, secure

	ICU_GRP_SEI (0x4) : System error interrupt

	ICU_GRP_REI (0x5) : RAM error interrupt

	The 2nd cell was the index of the interrupt in the ICU unit.

	The 3rd cell was the type of the interrupt. See arm,gic.txt for

	details.

Example:

icu: interrupt-controller@1e0000 {

	compatible = "marvell,cp110-icu";

	reg = <0x1e0000 0x440>;

	#interrupt-cells = <3>;

	interrupt-controller;

	msi-parent = <&gicp>;

};

node1 {

	interrupt-parent = <&icu>;

	interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;

};