Commit 28c46fee authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Consolidate condition for Wa_22011802037 



The workaround bounds for Wa_22011802037 are somewhat complex and are
replicated in several places throughout the code.  Pull the condition
out to a helper function to prevent mistakes if this condition needs to
change again in the future.

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-12-matthew.d.roper@intel.com
parent c9517783

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+1 −3
Original line number Diff line number Diff line
@@ -1617,9 +1617,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine, 
	 * Wa_22011802037: Prior to doing a reset, ensure CS is

	 * stopped, set ring stop bit and prefetch disable bit to halt CS

	 */

	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||

	    (GRAPHICS_VER(engine->i915) >= 11 &&

	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))

	if (intel_engine_reset_needs_wa_22011802037(engine->gt))

		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),

				      _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

+1 −3
Original line number Diff line number Diff line
@@ -3001,9 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) 
	 * Wa_22011802037: In addition to stopping the cs, we need

	 * to wait for any pending mi force wakeups

	 */

	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||

	    (GRAPHICS_VER(engine->i915) >= 11 &&

	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))

	if (intel_engine_reset_needs_wa_22011802037(engine->gt))

		intel_engine_wait_for_pending_mi_fw(engine);



	engine->execlists.reset_ccid = active_ccid(engine);

drivers/gpu/drm/i915/gt/intel_reset.c

+18 −0
Original line number Diff line number Diff line
@@ -1632,6 +1632,24 @@ void __intel_fini_wedge(struct intel_wedge_me *w) 
	w->gt = NULL;

}



/*

 * Wa_22011802037 requires that we (or the GuC) ensure that no command

 * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.

 */

bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)

{

	if (GRAPHICS_VER(gt->i915) < 11)

		return false;



	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))

		return true;



	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))

		return false;



	return true;

}



#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)

#include "selftest_reset.c"

#include "selftest_hangcheck.c"

drivers/gpu/drm/i915/gt/intel_reset.h

+2 −0
Original line number Diff line number Diff line
@@ -78,4 +78,6 @@ void __intel_fini_wedge(struct intel_wedge_me *w); 
bool intel_has_gpu_reset(const struct intel_gt *gt);

bool intel_has_reset_engine(const struct intel_gt *gt);



bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt);



#endif /* I915_RESET_H */

drivers/gpu/drm/i915/gt/uc/intel_guc.c

+1 −3
Original line number Diff line number Diff line
@@ -288,9 +288,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) 
		flags |= GUC_WA_DUAL_QUEUE;



	/* Wa_22011802037: graphics version 11/12 */

	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||

	    (GRAPHICS_VER(gt->i915) >= 11 &&

	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))

	if (intel_engine_reset_needs_wa_22011802037(gt))

		flags |= GUC_WA_PRE_PARSER;



	/*