Commit 2b3b9a8f authored by Suraj Kandpal's avatar Suraj Kandpal
Browse files

drm/i915/dpll: Move away from using shared dpll 



Rename functions to move away from using shared dpll in the dpll
framework as much as possible since dpll may not always be shared.

--v2
-Use intel_dpll_global instead of global_dpll [Jani]

--v3
-Just use intel_dpll [Jani]

--v4
-Drop the global from comments [Jani]

Signed-off-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/20250515071801.2221120-8-suraj.kandpal@intel.com
parent 386a1832

drivers/gpu/drm/i915/display/intel_ddi.c

+7 −7
Original line number Diff line number Diff line
@@ -1569,7 +1569,7 @@ _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, 


	id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;



	return intel_get_shared_dpll_by_id(display, id);

	return intel_get_dpll_by_id(display, id);

}



static void adls_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1723,7 +1723,7 @@ static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 
	if (phy >= PHY_C)

		id += DPLL_ID_DG1_DPLL2;



	return intel_get_shared_dpll_by_id(display, id);

	return intel_get_dpll_by_id(display, id);

}



static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
@@ -1895,7 +1895,7 @@ static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 
		return NULL;

	}



	return intel_get_shared_dpll_by_id(display, id);

	return intel_get_dpll_by_id(display, id);

}



static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
@@ -1918,7 +1918,7 @@ static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 
		return NULL;

	}



	return intel_get_shared_dpll_by_id(display, id);

	return intel_get_dpll_by_id(display, id);

}



static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1986,7 +1986,7 @@ static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 
	id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>

		DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);



	return intel_get_shared_dpll_by_id(display, id);

	return intel_get_dpll_by_id(display, id);

}



void hsw_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2053,7 +2053,7 @@ static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 
		return NULL;

	}



	return intel_get_shared_dpll_by_id(display, id);

	return intel_get_dpll_by_id(display, id);

}



void intel_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2760,7 +2760,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 
	 * 4. Enable the port PLL.

	 *

	 * The PLL enabling itself was already done before this function by

	 * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only

	 * hsw_crtc_enable()->intel_enable_dpll().  We need only

	 * configure the PLL to port mapping here.

	 */

	intel_ddi_enable_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

+4 −4
Original line number Diff line number Diff line
@@ -1664,7 +1664,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, 
	intel_encoders_pre_pll_enable(state, crtc);



	if (new_crtc_state->intel_dpll)

		intel_enable_shared_dpll(new_crtc_state);

		intel_enable_dpll(new_crtc_state);



	intel_encoders_pre_enable(state, crtc);
@@ -1793,7 +1793,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, 
	intel_encoders_disable(state, crtc);

	intel_encoders_post_disable(state, crtc);



	intel_disable_shared_dpll(old_crtc_state);

	intel_disable_dpll(old_crtc_state);



	intel_encoders_post_pll_disable(state, crtc);
@@ -6436,7 +6436,7 @@ int intel_atomic_check(struct drm_device *dev, 


		any_ms = true;



		intel_release_shared_dplls(state, crtc);

		intel_release_dplls(state, crtc);

	}



	if (any_ms && !check_digital_port_conflicts(state)) {
@@ -7533,7 +7533,7 @@ static int intel_atomic_swap_state(struct intel_atomic_state *state) 


	intel_atomic_swap_global_state(state);



	intel_shared_dpll_swap_state(state);

	intel_dpll_swap_state(state);



	intel_atomic_track_fbs(state);

drivers/gpu/drm/i915/display/intel_display_driver.c

+1 −1
Original line number Diff line number Diff line
@@ -446,7 +446,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display) 
	}



	intel_plane_possible_crtcs_init(display);

	intel_shared_dpll_init(display);

	intel_dpll_init(display);

	intel_fdi_pll_freq_update(display);



	intel_update_czclk(display);

drivers/gpu/drm/i915/display/intel_dpll.c

+5 −5
Original line number Diff line number Diff line
@@ -1162,7 +1162,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state, 
	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

		return 0;



	ret = intel_compute_shared_dplls(state, crtc, encoder);

	ret = intel_compute_dplls(state, crtc, encoder);

	if (ret)

		return ret;
@@ -1190,7 +1190,7 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, 
	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

		return 0;



	return intel_reserve_shared_dplls(state, crtc, encoder);

	return intel_reserve_dplls(state, crtc, encoder);

}



static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1224,7 +1224,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state, 
	if (ret)

		return ret;



	/* TODO: Do the readback via intel_compute_shared_dplls() */

	/* TODO: Do the readback via intel_compute_dplls() */

	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);



	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
@@ -1395,7 +1395,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, 
	ilk_compute_dpll(crtc_state, &crtc_state->dpll,

			 &crtc_state->dpll);



	ret = intel_compute_shared_dplls(state, crtc, NULL);

	ret = intel_compute_dplls(state, crtc, NULL);

	if (ret)

		return ret;
@@ -1415,7 +1415,7 @@ static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state, 
	if (!crtc_state->has_pch_encoder)

		return 0;



	return intel_reserve_shared_dplls(state, crtc, NULL);

	return intel_reserve_dplls(state, crtc, NULL);

}



static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+117 −118

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