Commit 2d0f3f13 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'nuvoton/newsoc' into arm/newsoc 

Merge the new SoC support from Tomer Maimon:
 "This patchset  adds initial support for the Nuvoton
  Arbel NPCM8XX Board Management controller (BMC) SoC family.

  The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC.
  The NPCM8XX computing subsystem comprises a quadcore ARM
  Cortex A35 ARM-V8 architecture.

  This patchset adds minimal architecture and drivers such as:
  Clocksource, Clock, Reset, and WD.

  Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.

  This patchset was tested on the Arbel NPCM8XX evaluation board."

I'm leaving out the clk controller driver, which is still under
review.

* nuvoton/newsoc:
  arm64: defconfig: Add Nuvoton NPCM family support
  arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
  arm64: dts: nuvoton: Add initial NPCM8XX device tree
  arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
  dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
  dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
  dt-bindings: arm: npcm: Add maintainer
  reset: npcm: Add NPCM8XX support
  dt-bindings: reset: npcm: Add support for NPCM8XX
  reset: npcm: using syscon instead of device data
  ARM: dts: nuvoton: add reset syscon property
  dt-bindings: reset: npcm: add GCR syscon property
  dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
  dt-bindings: watchdog: npcm: Add npcm845 compatible string
  dt-bindings: timer: npcm: Add npcm845 compatible string
parents 7cb7b8fe 45472f1e

Documentation/devicetree/bindings/arm/npcm/npcm.yaml

+7 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ title: NPCM Platforms Device Tree Bindings 


maintainers:

  - Jonathan Neuschäfer <j.neuschaefer@gmx.net>

  - Tomer Maimon <tmaimon77@gmail.com>



properties:

  $nodename:
@@ -26,4 +27,10 @@ properties: 
              - nuvoton,npcm750-evb         # NPCM750 evaluation board

          - const: nuvoton,npcm750



      - description: NPCM845 based boards

        items:

          - enum:

              - nuvoton,npcm845-evb         # NPCM845 evaluation board

          - const: nuvoton,npcm845



additionalProperties: true

Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml

+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ title: Global Control Registers block in Nuvoton SoCs 


maintainers:

  - Jonathan Neuschäfer <j.neuschaefer@gmx.net>

  - Tomer Maimon <tmaimon77@gmail.com>



description:

  The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs
@@ -20,6 +21,7 @@ properties: 
      - enum:

          - nuvoton,wpcm450-gcr

          - nuvoton,npcm750-gcr

          - nuvoton,npcm845-gcr

      - const: syscon

      - const: simple-mfd

Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml

0 → 100644
+49 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Nuvoton NPCM8XX Clock Controller Binding



maintainers:

  - Tomer Maimon <tmaimon77@gmail.com>



description: |

  Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which

  generates and supplies clocks to all modules within the BMC.



properties:

  compatible:

    enum:

      - nuvoton,npcm845-clk



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1

    description:

      See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full

      list of NPCM8XX clock IDs.



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    ahb {

        #address-cells = <2>;

        #size-cells = <2>;



        clock-controller@f0801000 {

            compatible = "nuvoton,npcm845-clk";

            reg = <0x0 0xf0801000 0x0 0x1000>;

            #clock-cells = <1>;

        };

    };

...

Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml

+9 −1
Original line number Diff line number Diff line
@@ -11,7 +11,9 @@ maintainers: 


properties:

  compatible:

    const: nuvoton,npcm750-reset

    enum:

      - nuvoton,npcm750-reset        # Poleg NPCM7XX SoC

      - nuvoton,npcm845-reset        # Arbel NPCM8XX SoC



  reg:

    maxItems: 1
@@ -19,6 +21,10 @@ properties: 
  '#reset-cells':

    const: 2



  nuvoton,sysgcr:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: a phandle to access GCR registers.



  nuvoton,sw-reset-number:

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 1
@@ -31,6 +37,7 @@ required: 
  - compatible

  - reg

  - '#reset-cells'

  - nuvoton,sysgcr



additionalProperties: false
@@ -41,6 +48,7 @@ examples: 
        compatible = "nuvoton,npcm750-reset";

        reg = <0xf0801000 0x70>;

        #reset-cells = <2>;

        nuvoton,sysgcr = <&gcr>;

        nuvoton,sw-reset-number = <2>;

    };

Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml

+2 −0
Original line number Diff line number Diff line
@@ -8,12 +8,14 @@ title: Nuvoton NPCM7xx timer 


maintainers:

  - Jonathan Neuschäfer <j.neuschaefer@gmx.net>

  - Tomer Maimon <tmaimon77@gmail.com>



properties:

  compatible:

    enum:

      - nuvoton,wpcm450-timer  # for Hermon WPCM450

      - nuvoton,npcm750-timer  # for Poleg NPCM750

      - nuvoton,npcm845-timer  # for Arbel NPCM845



  reg:

    maxItems: 1