Commit 30eccd3b authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/stm32' 

- Update pinctrl documentation of initial states and use in runtime
  suspend/resume (Christian Bruel)

- Add pinctrl_pm_select_init_state() for use by stm32 driver, which needs
  it during resume (Christian Bruel)

- Add devicetree bindings and drivers for the STMicroelectronics STM32MP25
  in host and endpoint modes (Christian Bruel)

* pci/controller/stm32:
  MAINTAINERS: Add entry for ST STM32MP25 PCIe drivers
  PCI: stm32-ep: Add PCIe Endpoint support for STM32MP25
  dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings
  PCI: stm32: Add PCIe host support for STM32MP25
  dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings
  pinctrl: Add pinctrl_pm_select_init_state helper function
  Documentation: pinctrl: Describe PM helper functions for standard states.
parents 0157e111 c86a24df

Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/st,stm32-pcie-common.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: STM32MP25 PCIe RC/EP controller



maintainers:

  - Christian Bruel <christian.bruel@foss.st.com>



description:

  STM32MP25 PCIe RC/EP common properties



properties:

  clocks:

    maxItems: 1

    description: PCIe system clock



  resets:

    maxItems: 1



  power-domains:

    maxItems: 1



  access-controllers:

    maxItems: 1



required:

  - clocks

  - resets



additionalProperties: true

Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: STMicroelectronics STM32MP25 PCIe Endpoint



maintainers:

  - Christian Bruel <christian.bruel@foss.st.com>



description:

  PCIe endpoint controller based on the Synopsys DesignWare PCIe core.



allOf:

  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#

  - $ref: /schemas/pci/st,stm32-pcie-common.yaml#



properties:

  compatible:

    const: st,stm32mp25-pcie-ep



  reg:

    items:

      - description: Data Bus Interface (DBI) registers.

      - description: Data Bus Interface (DBI) shadow registers.

      - description: Internal Address Translation Unit (iATU) registers.

      - description: PCIe configuration registers.



  reg-names:

    items:

      - const: dbi

      - const: dbi2

      - const: atu

      - const: addr_space



  reset-gpios:

    description: GPIO controlled connection to PERST# signal

    maxItems: 1



  phys:

    maxItems: 1



required:

  - phys

  - reset-gpios



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/st,stm32mp25-rcc.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/phy/phy.h>

    #include <dt-bindings/reset/st,stm32mp25-rcc.h>



    pcie-ep@48400000 {

        compatible = "st,stm32mp25-pcie-ep";

        reg = <0x48400000 0x400000>,

              <0x48500000 0x100000>,

              <0x48700000 0x80000>,

              <0x10000000 0x10000000>;

        reg-names = "dbi", "dbi2", "atu", "addr_space";

        clocks = <&rcc CK_BUS_PCIE>;

        phys = <&combophy PHY_TYPE_PCIE>;

        resets = <&rcc PCIE_R>;

        pinctrl-names = "default", "init";

        pinctrl-0 = <&pcie_pins_a>;

        pinctrl-1 = <&pcie_init_pins_a>;

        reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;

        access-controllers = <&rifsc 68>;

        power-domains = <&CLUSTER_PD>;

    };

Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: STMicroelectronics STM32MP25 PCIe Root Complex



maintainers:

  - Christian Bruel <christian.bruel@foss.st.com>



description:

  PCIe root complex controller based on the Synopsys DesignWare PCIe core.



allOf:

  - $ref: /schemas/pci/snps,dw-pcie.yaml#

  - $ref: /schemas/pci/st,stm32-pcie-common.yaml#



properties:

  compatible:

    const: st,stm32mp25-pcie-rc



  reg:

    items:

      - description: Data Bus Interface (DBI) registers.

      - description: PCIe configuration registers.



  reg-names:

    items:

      - const: dbi

      - const: config



  msi-parent:

    maxItems: 1



patternProperties:

  '^pcie@[0-2],0$':

    type: object

    $ref: /schemas/pci/pci-pci-bridge.yaml#



    properties:

      reg:

        maxItems: 1



      phys:

        maxItems: 1



      reset-gpios:

        description: GPIO controlled connection to PERST# signal

        maxItems: 1



      wake-gpios:

        description: GPIO used as WAKE# input signal

        maxItems: 1



    required:

      - phys

      - ranges



    unevaluatedProperties: false



required:

  - interrupt-map

  - interrupt-map-mask

  - ranges

  - dma-ranges



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/st,stm32mp25-rcc.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/phy/phy.h>

    #include <dt-bindings/reset/st,stm32mp25-rcc.h>



    pcie@48400000 {

        compatible = "st,stm32mp25-pcie-rc";

        device_type = "pci";

        reg = <0x48400000 0x400000>,

              <0x10000000 0x10000>;

        reg-names = "dbi", "config";

        #interrupt-cells = <1>;

        interrupt-map-mask = <0 0 0 7>;

        interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,

                        <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,

                        <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,

                        <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;

        #address-cells = <3>;

        #size-cells = <2>;

        ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>,

                 <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>,

                 <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>;

        dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>;

        clocks = <&rcc CK_BUS_PCIE>;

        resets = <&rcc PCIE_R>;

        msi-parent = <&v2m0>;

        access-controllers = <&rifsc 68>;

        power-domains = <&CLUSTER_PD>;



        pcie@0,0 {

            device_type = "pci";

            reg = <0x0 0x0 0x0 0x0 0x0>;

            phys = <&combophy PHY_TYPE_PCIE>;

            wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;

            reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;

            #address-cells = <3>;

            #size-cells = <2>;

            ranges;

        };

    };

Documentation/driver-api/pin-control.rst

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@@ -1162,8 +1162,55 @@ pinmux core. 
Pin control requests from drivers

=================================



When a device driver is about to probe the device core will automatically

attempt to issue ``pinctrl_get_select_default()`` on these devices.

When a device driver is about to probe, the device core attaches the

standard states if they are defined in the device tree by calling

``pinctrl_bind_pins()`` on these devices.

Possible standard state names are: "default", "init", "sleep" and "idle".



- if ``default`` is defined in the device tree, it is selected before

  device probe.



- if ``init`` and ``default`` are defined in the device tree, the "init"

  state is selected before the driver probe and the "default" state is

  selected after the driver probe.



- the ``sleep`` and ``idle`` states are for power management and can only

  be selected with the PM API bellow.



PM interfaces

=================

PM runtime suspend/resume might need to execute the same init sequence as

during probe. Since the predefined states are already attached to the

device, the driver can activate these states explicitly with the

following helper functions:



- ``pinctrl_pm_select_default_state()``

- ``pinctrl_pm_select_init_state()``

- ``pinctrl_pm_select_sleep_state()``

- ``pinctrl_pm_select_idle_state()``



For example, if resuming the device depend on certain pinmux states



.. code-block:: c



	foo_suspend()

	{

		/* suspend device */

		...



		pinctrl_pm_select_sleep_state(dev);

	}



	foo_resume()

	{

		pinctrl_pm_select_init_state(dev);



		/* resuming device */

		...



		pinctrl_pm_select_default_state(dev);

	}



This way driver writers do not need to add any of the boilerplate code

of the type found below. However when doing fine-grained state selection

and not using the "default" state, you may have to do some device driver
@@ -1185,6 +1232,12 @@ operation and going to sleep, moving from the ``PINCTRL_STATE_DEFAULT`` to 
``PINCTRL_STATE_SLEEP`` at runtime, re-biasing or even re-muxing pins to save

current in sleep mode.



Another case is when the pinctrl needs to switch to a certain mode during

probe and then revert to the default state at the end of probe. For example

a PINMUX may need to be configured as a GPIO during probe. In this case, use

``PINCTRL_STATE_INIT`` to switch state before probe, then move to

``PINCTRL_STATE_DEFAULT`` at the end of probe for normal operation.



A driver may request a certain control state to be activated, usually just the

default state like this:

MAINTAINERS

+7 −0
Original line number Diff line number Diff line
@@ -19377,6 +19377,13 @@ L: linux-samsung-soc@vger.kernel.org 
S:	Maintained

F:	drivers/pci/controller/dwc/pci-exynos.c









PCI DRIVER FOR STM32MP25









M:	Christian Bruel <christian.bruel@foss.st.com>









L:	linux-pci@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/pci/st,stm32-pcie-*.yaml









F:	drivers/pci/controller/dwc/*stm32*

















PCI DRIVER FOR SYNOPSYS DESIGNWARE









M:	Jingoo Han <jingoohan1@gmail.com>









M:	Manivannan Sadhasivam <mani@kernel.org>