Commit 316f4b91 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-parent', 'clk-renesas', 'clk-mediatek' and 'clk-cleanup' into clk-next 

* clk-parent:
  clk: check for disabled clock-provider in of_clk_get_hw_from_clkspec()

* clk-renesas: (24 commits)
  clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP
  clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1
  clk: renesas: r7s9210: Distinguish clocks by clock type
  clk: renesas: rzg2l: Remove unneeded nullify checks
  clk: renesas: cpg-mssr: Remove obsolete nullify check
  clk: renesas: r9a09g057: Add entries for the DMACs
  clk: renesas: r9a09g047: Add CANFD clocks and resets
  clk: renesas: r9a09g047: Add CRU0 clocks and resets
  clk: renesas: rzv2h: Update error message
  clk: renesas: rzg2l: Update error message
  clk: renesas: r9a09g047: Add ICU clock/reset
  clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
  clk: renesas: r9a09g047: Add SDHI clocks/resets
  clk: renesas: r8a779h0: Add VSPX clock
  clk: renesas: r8a779h0: Add FCPVX clock
  clk: renesas: r8a08g045: Check the source of the CPU PLL settings
  clk: renesas: r9a09g047: Add WDT clocks and resets
  clk: renesas: r8a779h0: Add ISP core clocks
  clk: renesas: r8a779g0: Add ISP core clocks
  clk: renesas: r8a779a0: Add ISP core clocks
  ...

* clk-mediatek:
  clk: mediatek: Add SMI LARBs reset for MT8188
  dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188
  clk: mediatek: mt8188-vdo1: Add VDO1_DPI1_HDMI clock for hdmitx
  dt-bindings: clock: mediatek,mt8188: Add VDO1_DPI1_HDMI clock

* clk-cleanup:
  dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles
  clk: davinci: remove support for da830
  dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema
  clk: mmp: Fix NULL vs IS_ERR() check
  clk: Print an error when clk registration fails
  clk: Correct the data types of the variables in clk_calc_new_rates
  clk: imgtec: use %pe for better readability of errors while printing
  clk: stm32f4: fix an uninitialized variable
  clk: keystone: syscon-clk: Do not use syscon helper to build regmap
parents b20150d4 fca77a6b 0ca0dc89 86484e08

Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml

+4 −0
Original line number Diff line number Diff line
@@ -34,6 +34,8 @@ properties: 
          - enum:

              - atmel,at91rm9200-pmc

              - atmel,at91sam9260-pmc

              - atmel,at91sam9261-pmc

              - atmel,at91sam9263-pmc

              - atmel,at91sam9g45-pmc

              - atmel,at91sam9n12-pmc

              - atmel,at91sam9rl-pmc
@@ -111,6 +113,8 @@ allOf: 
            enum:

              - atmel,at91rm9200-pmc

              - atmel,at91sam9260-pmc

              - atmel,at91sam9261-pmc

              - atmel,at91sam9263-pmc

              - atmel,at91sam9g20-pmc

    then:

      properties:

Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml

+21 −0
Original line number Diff line number Diff line
@@ -57,6 +57,27 @@ required: 
  - reg

  - '#clock-cells'



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - mediatek,mt8188-camsys-rawa

              - mediatek,mt8188-camsys-rawb

              - mediatek,mt8188-camsys-yuva

              - mediatek,mt8188-camsys-yuvb

              - mediatek,mt8188-imgsys-wpe1

              - mediatek,mt8188-imgsys-wpe2

              - mediatek,mt8188-imgsys-wpe3

              - mediatek,mt8188-imgsys1-dip-nr

              - mediatek,mt8188-imgsys1-dip-top

              - mediatek,mt8188-ipesys



    then:

      required:

        - '#reset-cells'



additionalProperties: false



examples:

Documentation/devicetree/bindings/clock/ti,clkctrl.yaml

0 → 100644
+65 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/ti,clkctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Texas Instruments clkctrl clock



maintainers:

  - Tony Lindgren <tony@atomide.com>

  - Andreas Kemnade <andreas@kemnade.info>



description: |

  Texas Instruments SoCs can have a clkctrl clock controller for each

  interconnect target module. The clkctrl clock controller manages functional

  and interface clocks for each module. Each clkctrl controller can also

  gate one or more optional functional clocks for a module, and can have one

  or more clock muxes. There is a clkctrl clock controller typically for each

  interconnect target module on omap4 and later variants.



  The clock consumers can specify the index of the clkctrl clock using

  the hardware offset from the clkctrl instance register space. The optional

  clocks can be specified by clkctrl hardware offset and the index of the

  optional clock.



properties:

  compatible:

    enum:

      - ti,clkctrl

      - ti,clkctrl-l4-cfg

      - ti,clkctrl-l4-per

      - ti,clkctrl-l4-secure

      - ti,clkctrl-l4-wkup



  "#clock-cells":

    const: 2



  clock-output-names:

    maxItems: 1



  reg:

    minItems: 1

    maxItems: 8 # arbitrary, should be enough



required:

  - compatible

  - "#clock-cells"

  - clock-output-names

  - reg



additionalProperties: false



examples:

  - |

    bus {

      #address-cells = <1>;

      #size-cells = <1>;



      clock@20 {

        compatible = "ti,clkctrl";

        clock-output-names = "l4_per";

        reg = <0x20 0x1b0>;

        #clock-cells = <2>;

      };

    };

Documentation/devicetree/bindings/clock/ti-clkctrl.txt

deleted100644 → 0
+0 −63
Original line number Diff line number Diff line 
Texas Instruments clkctrl clock binding



Texas Instruments SoCs can have a clkctrl clock controller for each

interconnect target module. The clkctrl clock controller manages functional

and interface clocks for each module. Each clkctrl controller can also

gate one or more optional functional clocks for a module, and can have one

or more clock muxes. There is a clkctrl clock controller typically for each

interconnect target module on omap4 and later variants.



The clock consumers can specify the index of the clkctrl clock using

the hardware offset from the clkctrl instance register space. The optional

clocks can be specified by clkctrl hardware offset and the index of the

optional clock.



For more information, please see the Linux clock framework binding at

Documentation/devicetree/bindings/clock/clock-bindings.txt.



Required properties :

- compatible : shall be "ti,clkctrl" or a clock domain specific name:

	       "ti,clkctrl-l4-cfg"

	       "ti,clkctrl-l4-per"

	       "ti,clkctrl-l4-secure"

	       "ti,clkctrl-l4-wkup"

- clock-output-names : from common clock binding

- #clock-cells : shall contain 2 with the first entry being the instance

		 offset from the clock domain base and the second being the

		 clock index

- reg : clock registers



Example: Clock controller node on omap 4430:



&cm2 {

	l4per: cm@1400 {

		cm_l4per@0 {

			cm_l4per_clkctrl: clock@20 {

				compatible = "ti,clkctrl";

				clock-output-names = "l4_per";

				reg = <0x20 0x1b0>;

				#clock-cells = <2>;

			};

		};

	};

};



Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h



#define OMAP4_CLKCTRL_OFFSET		0x20

#define OMAP4_CLKCTRL_INDEX(offset)	((offset) - OMAP4_CLKCTRL_OFFSET)

#define MODULEMODE_HWCTRL		1

#define MODULEMODE_SWCTRL		2



#define OMAP4_GPTIMER10_CLKTRL		OMAP4_CLKCTRL_INDEX(0x28)

#define OMAP4_GPTIMER11_CLKTRL		OMAP4_CLKCTRL_INDEX(0x30)

#define OMAP4_GPTIMER2_CLKTRL		OMAP4_CLKCTRL_INDEX(0x38)

...

#define OMAP4_GPIO2_CLKCTRL		OMAP_CLKCTRL_INDEX(0x60)



Example: Clock consumer node for GPIO2:



&gpio2 {

       clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0

		 &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;

};

drivers/clk/clk-stm32f4.c

+2 −2
Original line number Diff line number Diff line
@@ -888,7 +888,6 @@ static int __init stm32f4_pll_ssc_parse_dt(struct device_node *np, 
					   struct stm32f4_pll_ssc *conf)

{

	int ret;

	const char *s;



	if (!conf)

		return -EINVAL;
@@ -916,7 +915,8 @@ static int __init stm32f4_pll_ssc_parse_dt(struct device_node *np, 
	conf->mod_type = ret;



	pr_debug("%pOF: SSCG settings: mod_freq: %d, mod_depth: %d mod_method: %s [%d]\n",

		 np, conf->mod_freq, conf->mod_depth, s, conf->mod_type);

		 np, conf->mod_freq, conf->mod_depth,

		 stm32f4_ssc_mod_methods[ret], conf->mod_type);



	return 0;

}