Commit fca77a6b authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.15-tag2' of... 

Merge tag 'renesas-clk-for-v6.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull more Renesas clk driver updates from Geert Uytterhoeven:

 - Add DMA clocks and reset on Renesas RZ/V2H
 - Add thermal (TSU) clock and reset on Renesas RZ/G3E

* tag 'renesas-clk-for-v6.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP
  clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1
  clk: renesas: r7s9210: Distinguish clocks by clock type
  clk: renesas: rzg2l: Remove unneeded nullify checks
  clk: renesas: cpg-mssr: Remove obsolete nullify check
  clk: renesas: r9a09g057: Add entries for the DMACs
parents a0e2025f e1a09833

drivers/clk/renesas/r7s9210-cpg-mssr.c

+4 −6
Original line number Diff line number Diff line
@@ -170,11 +170,12 @@ static struct clk * __init rza2_cpg_clk_register(struct device *dev, 
	if (IS_ERR(parent))

		return ERR_CAST(parent);



	switch (core->id) {

	case CLK_MAIN:

	switch (core->type) {

	case CLK_TYPE_RZA_MAIN:

		r7s9210_update_clk_table(parent, base);

		break;



	case CLK_PLL:

	case CLK_TYPE_RZA_PLL:

		if (cpg_mode)

			mult = 44;	/* Divider 1 is 1/2 */

		else
@@ -185,9 +186,6 @@ static struct clk * __init rza2_cpg_clk_register(struct device *dev, 
		return ERR_PTR(-EINVAL);

	}



	if (core->id == CLK_MAIN)

		r7s9210_update_clk_table(parent, base);



	return clk_register_fixed_factor(NULL, core->name,

					 __clk_get_name(parent), 0, mult, div);

}

drivers/clk/renesas/r9a09g047-cpg.c

+3 −0
Original line number Diff line number Diff line
@@ -183,6 +183,8 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { 
						BUS_MSTOP(9, BIT(4))),

	DEF_MOD("cru_0_pclk",			CLK_PLLDTY_DIV16, 13, 4, 6, 20,

						BUS_MSTOP(9, BIT(4))),

	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,

						BUS_MSTOP(2, BIT(15))),

};



static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
@@ -211,6 +213,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { 
	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */

	DEF_RST(12, 6, 5, 23),		/* CRU_0_ARESETN */

	DEF_RST(12, 7, 5, 24),		/* CRU_0_S_RESETN */

	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */

};



const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {

drivers/clk/renesas/r9a09g057-cpg.c

+24 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ enum clk_ids { 
	CLK_PLLVDO,



	/* Internal Core Clocks */

	CLK_PLLCM33_DIV4,

	CLK_PLLCM33_DIV4_PLLCM33,

	CLK_PLLCM33_DIV16,

	CLK_PLLCLN_DIV2,

	CLK_PLLCLN_DIV8,
@@ -39,6 +41,8 @@ enum clk_ids { 
	CLK_PLLDTY_ACPU_DIV2,

	CLK_PLLDTY_ACPU_DIV4,

	CLK_PLLDTY_DIV16,

	CLK_PLLDTY_RCPU,

	CLK_PLLDTY_RCPU_DIV4,

	CLK_PLLVDO_CRU0,

	CLK_PLLVDO_CRU1,

	CLK_PLLVDO_CRU2,
@@ -85,6 +89,9 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
	DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),



	/* Internal Core Clocks */

	DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),

	DEF_DDIV(".pllcm33_div4_pllcm33", CLK_PLLCM33_DIV4_PLLCM33,

		 CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),

	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),



	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
@@ -95,6 +102,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),

	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),

	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),

	DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),

	DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),



	DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),

	DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
@@ -115,6 +124,16 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
};



static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {

	DEF_MOD("dmac_0_aclk",			CLK_PLLCM33_DIV4_PLLCM33, 0, 0, 0, 0,

						BUS_MSTOP(5, BIT(9))),

	DEF_MOD("dmac_1_aclk",			CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,

						BUS_MSTOP(3, BIT(2))),

	DEF_MOD("dmac_2_aclk",			CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,

						BUS_MSTOP(3, BIT(3))),

	DEF_MOD("dmac_3_aclk",			CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,

						BUS_MSTOP(10, BIT(11))),

	DEF_MOD("dmac_4_aclk",			CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,

						BUS_MSTOP(10, BIT(12))),

	DEF_MOD_CRITICAL("icu_0_pclk_i",	CLK_PLLCM33_DIV16, 0, 5, 0, 5,

						BUS_MSTOP_NONE),

	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
@@ -223,6 +242,11 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 


static const struct rzv2h_reset r9a09g057_resets[] __initconst = {

	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */

	DEF_RST(3, 1, 1, 2),		/* DMAC_0_ARESETN */

	DEF_RST(3, 2, 1, 3),		/* DMAC_1_ARESETN */

	DEF_RST(3, 3, 1, 4),		/* DMAC_2_ARESETN */

	DEF_RST(3, 4, 1, 5),		/* DMAC_3_ARESETN */

	DEF_RST(3, 5, 1, 6),		/* DMAC_4_ARESETN */

	DEF_RST(3, 6, 1, 7),		/* ICU_0_PRESETN_I */

	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */

	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */

drivers/clk/renesas/renesas-cpg-mssr.c

+0 −5
Original line number Diff line number Diff line
@@ -338,11 +338,6 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, 
	WARN_DEBUG(id >= priv->num_core_clks);

	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);



	if (!core->name) {

		/* Skip NULLified clock */

		return;

	}



	switch (core->type) {

	case CLK_TYPE_IN:

		clk = of_clk_get_by_name(priv->np, core->name);

drivers/clk/renesas/rzg2l-cpg.c

+0 −10
Original line number Diff line number Diff line
@@ -1116,11 +1116,6 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, 
	WARN_DEBUG(id >= priv->num_core_clks);

	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);



	if (!core->name) {

		/* Skip NULLified clock */

		return;

	}



	switch (core->type) {

	case CLK_TYPE_IN:

		clk = of_clk_get_by_name(priv->dev->of_node, core->name);
@@ -1355,11 +1350,6 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, 
	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);

	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);



	if (!mod->name) {

		/* Skip NULLified clock */

		return;

	}



	parent = priv->clks[mod->parent];

	if (IS_ERR(parent)) {

		clk = parent;