Commit 326e30e4 authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915: Drop dead code for pvc 



PCI IDs for PVC were never added and platform always marked with
force_probe. Drop what's not used and rename some places as needed.

The registers not used anymore are also removed.

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: default avatarTvrtko Ursulin <tursulin@ursulin.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20240320060543.4034215-6-lucas.demarchi@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 48ba4a6d

drivers/gpu/drm/i915/gem/i915_gem_object_types.h

+1 −1
Original line number Diff line number Diff line
@@ -386,7 +386,7 @@ struct drm_i915_gem_object { 
	 * and kernel mode driver for caching policy control after GEN12.

	 * In the meantime platform specific tables are created to translate

	 * i915_cache_level into pat index, for more details check the macros

	 * defined i915/i915_pci.c, e.g. PVC_CACHELEVEL.

	 * defined i915/i915_pci.c, e.g. TGL_CACHELEVEL.

	 * For backward compatibility, this field contains values exactly match

	 * the entries of enum i915_cache_level for pre-GEN12 platforms (See

	 * LEGACY_CACHELEVEL), so that the PTE encode functions for these

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+0 −3
Original line number Diff line number Diff line
@@ -189,9 +189,6 @@ static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs *engine) 
{

	i915_reg_t reg = gen12_get_aux_inv_reg(engine);



	if (IS_PONTEVECCHIO(engine->i915))

		return false;



	/*

	 * So far platforms supported by i915 having flat ccs do not require

	 * AUX invalidation. Check also whether the engine requires it.

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+0 −33
Original line number Diff line number Diff line
@@ -839,38 +839,6 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt) 
	}

}



static void engine_mask_apply_copy_fuses(struct intel_gt *gt)

{

	struct drm_i915_private *i915 = gt->i915;

	struct intel_gt_info *info = &gt->info;

	unsigned long meml3_mask;

	unsigned long quad;



	if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&

	      GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))

		return;



	meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);

	meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);



	/*

	 * Link Copy engines may be fused off according to meml3_mask. Each

	 * bit is a quad that houses 2 Link Copy and two Sub Copy engines.

	 */

	for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {

		unsigned int instance = quad * 2 + 1;

		intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),

						   _BCS(instance));



		if (mask & info->engine_mask) {

			gt_dbg(gt, "bcs%u fused off\n", instance);

			gt_dbg(gt, "bcs%u fused off\n", instance + 1);



			info->engine_mask &= ~mask;

		}

	}

}



/*

 * Determine which engines are fused off in our particular hardware.

 * Note that we have a catch-22 situation where we need to be able to access
@@ -889,7 +857,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 


	engine_mask_apply_media_fuses(gt);

	engine_mask_apply_compute_fuses(gt);

	engine_mask_apply_copy_fuses(gt);



	/*

	 * The only use of the GSC CS is to load and communicate with the GSC

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

+1 −29
Original line number Diff line number Diff line
@@ -69,27 +69,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = { 
	{},

};



/*

 * We have several types of MCR registers on PVC where steering to (0,0)

 * will always provide us with a non-terminated value.  We'll stick them

 * all in the same table for simplicity.

 */

static const struct intel_mmio_range pvc_instance0_steering_table[] = {

	{ 0x004000, 0x004AFF },		/* HALF-BSLICE */

	{ 0x008800, 0x00887F },		/* CC */

	{ 0x008A80, 0x008AFF },		/* TILEPSMI */

	{ 0x00B000, 0x00B0FF },		/* HALF-BSLICE */

	{ 0x00B100, 0x00B3FF },		/* L3BANK */

	{ 0x00C800, 0x00CFFF },		/* HALF-BSLICE */

	{ 0x00D800, 0x00D8FF },		/* HALF-BSLICE */

	{ 0x00DD00, 0x00DDFF },		/* BSLICE */

	{ 0x00E900, 0x00E9FF },		/* HALF-BSLICE */

	{ 0x00EC00, 0x00EEFF },		/* HALF-BSLICE */

	{ 0x00F000, 0x00FFFF },		/* HALF-BSLICE */

	{ 0x024180, 0x0241FF },		/* HALF-BSLICE */

	{},

};



static const struct intel_mmio_range xelpg_instance0_steering_table[] = {

	{ 0x000B00, 0x000BFF },         /* SQIDI */

	{ 0x001000, 0x001FFF },         /* SQIDI */
@@ -173,8 +152,6 @@ void intel_gt_mcr_init(struct intel_gt *gt) 
		gt->steering_table[INSTANCE0] = xelpg_instance0_steering_table;

		gt->steering_table[L3BANK] = xelpg_l3bank_steering_table;

		gt->steering_table[DSS] = xelpg_dss_steering_table;

	} else if (IS_PONTEVECCHIO(i915)) {

		gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;

	} else if (IS_DG2(i915)) {

		gt->steering_table[MSLICE] = dg2_mslice_steering_table;

		gt->steering_table[LNCF] = dg2_lncf_steering_table;
@@ -805,8 +782,6 @@ void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt, 
		for (int i = 0; i < NUM_STEERING_TYPES; i++)

			if (gt->steering_table[i])

				report_steering_type(p, gt, i, dump_table);

	} else if (IS_PONTEVECCHIO(gt->i915)) {

		report_steering_type(p, gt, INSTANCE0, dump_table);

	} else if (HAS_MSLICE_STEERING(gt->i915)) {

		report_steering_type(p, gt, MSLICE, dump_table);

		report_steering_type(p, gt, LNCF, dump_table);
@@ -826,10 +801,7 @@ void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt, 
void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,

				   unsigned int *group, unsigned int *instance)

{

	if (IS_PONTEVECCHIO(gt->i915)) {

		*group = dss / GEN_DSS_PER_CSLICE;

		*instance = dss % GEN_DSS_PER_CSLICE;

	} else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {

	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {

		*group = dss / GEN_DSS_PER_GSLICE;

		*instance = dss % GEN_DSS_PER_GSLICE;

	} else {

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+0 −9
Original line number Diff line number Diff line
@@ -953,10 +953,6 @@ 
#define   GEN7_WA_FOR_GEN7_L3_CONTROL		0x3C47FF8C

#define   GEN7_L3AGDIS				(1 << 19)



#define XEHPC_LNCFMISCCFGREG0			MCR_REG(0xb01c)

#define   XEHPC_HOSTCACHEEN			REG_BIT(1)

#define   XEHPC_OVRLSCCC			REG_BIT(0)



#define GEN7_L3CNTLREG2				_MMIO(0xb020)



/* MOCS (Memory Object Control State) registers */
@@ -1013,11 +1009,6 @@ 
#define XEHP_L3SCQREG7				MCR_REG(0xb188)

#define   BLEND_FILL_CACHING_OPT_DIS		REG_BIT(3)



#define XEHPC_L3SCRUB				MCR_REG(0xb18c)

#define   SCRUB_CL_DWNGRADE_SHARED		REG_BIT(12)

#define   SCRUB_RATE_PER_BANK_MASK		REG_GENMASK(2, 0)

#define   SCRUB_RATE_4B_PER_CLK			REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)



#define GEN11_GLBLINVL				_MMIO(0xb404)

#define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x7f << 5)

#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 5)