Commit 4717ccad authored by Ye Li's avatar Ye Li Committed by Abel Vesa
Browse files

clk: imx: composite-7ulp: Check the PCC present bit 



When some module is disabled by fuse, its PCC PR bit is default 0 and
PCC is not operational. Any write to this PCC will cause SError.

Fixes: b40ba806 ("clk: imx: Update the compsite driver to support imx8ulp")
Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarYe Li <ye.li@nxp.com>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240607133347.3291040-4-peng.fan@oss.nxp.com


Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
parent d342df11

drivers/clk/imx/clk-composite-7ulp.c

+7 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include "../clk-fractional-divider.h"

#include "clk.h"



#define PCG_PR_MASK		BIT(31)

#define PCG_PCS_SHIFT	24

#define PCG_PCS_MASK	0x7

#define PCG_CGC_SHIFT	30
@@ -78,6 +79,12 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, 
	struct clk_hw *hw;

	u32 val;



	val = readl(reg);

	if (!(val & PCG_PR_MASK)) {

		pr_info("PCC PR is 0 for clk:%s, bypass\n", name);

		return 0;

	}



	if (mux_present) {

		mux = kzalloc(sizeof(*mux), GFP_KERNEL);

		if (!mux)