Commit 47cf96fb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 updates from Will Deacon:
 "The headline feature is the re-enablement of support for Arm's
  Scalable Matrix Extension (SME) thanks to a bumper crop of fixes
  from Mark Rutland.

  If matrices aren't your thing, then Ryan's page-table optimisation
  work is much more interesting.

  Summary:

  ACPI, EFI and PSCI:

   - Decouple Arm's "Software Delegated Exception Interface" (SDEI)
     support from the ACPI GHES code so that it can be used by platforms
     booted with device-tree

   - Remove unnecessary per-CPU tracking of the FPSIMD state across EFI
     runtime calls

   - Fix a node refcount imbalance in the PSCI device-tree code

  CPU Features:

   - Ensure register sanitisation is applied to fields in ID_AA64MMFR4

   - Expose AIDR_EL1 to userspace via sysfs, primarily so that KVM
     guests can reliably query the underlying CPU types from the VMM

   - Re-enabling of SME support (CONFIG_ARM64_SME) as a result of fixes
     to our context-switching, signal handling and ptrace code

  Entry code:

   - Hook up TIF_NEED_RESCHED_LAZY so that CONFIG_PREEMPT_LAZY can be
     selected

  Memory management:

   - Prevent BSS exports from being used by the early PI code

   - Propagate level and stride information to the low-level TLB
     invalidation routines when operating on hugetlb entries

   - Use the page-table contiguous hint for vmap() mappings with
     VM_ALLOW_HUGE_VMAP where possible

   - Optimise vmalloc()/vmap() page-table updates to use "lazy MMU mode"
     and hook this up on arm64 so that the trailing DSB (used to publish
     the updates to the hardware walker) can be deferred until the end
     of the mapping operation

   - Extend mmap() randomisation for 52-bit virtual addresses (on par
     with 48-bit addressing) and remove limited support for
     randomisation of the linear map

  Perf and PMUs:

   - Add support for probing the CMN-S3 driver using ACPI

   - Minor driver fixes to the CMN, Arm-NI and amlogic PMU drivers

  Selftests:

   - Fix FPSIMD and SME tests to align with the freshly re-enabled SME
     support

   - Fix default setting of the OUTPUT variable so that tests are
     installed in the right location

  vDSO:

   - Replace raw counter access from inline assembly code with a call to
     the the __arch_counter_get_cntvct() helper function

  Miscellaneous:

   - Add some missing header inclusions to the CCA headers

   - Rework rendering of /proc/cpuinfo to follow the x86-approach and
     avoid repeated buffer expansion (the user-visible format remains
     identical)

   - Remove redundant selection of CONFIG_CRC32

   - Extend early error message when failing to map the device-tree
     blob"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (83 commits)
  arm64: cputype: Add cputype definition for HIP12
  arm64: el2_setup.h: Make __init_el2_fgt labels consistent, again
  perf/arm-cmn: Add CMN S3 ACPI binding
  arm64/boot: Disallow BSS exports to startup code
  arm64/boot: Move global CPU override variables out of BSS
  arm64/boot: Move init_pgdir[] and init_idmap_pgdir[] into __pi_ namespace
  perf/arm-cmn: Initialise cmn->cpu earlier
  kselftest/arm64: Set default OUTPUT path when undefined
  arm64: Update comment regarding values in __boot_cpu_mode
  arm64: mm: Drop redundant check in pmd_trans_huge()
  arm64/mm: Re-organise setting up FEAT_S1PIE registers PIRE0_EL1 and PIR_EL1
  arm64/mm: Permit lazy_mmu_mode to be nested
  arm64/mm: Disable barrier batching in interrupt contexts
  arm64/cpuinfo: only show one cpu's info in c_show()
  arm64/mm: Batch barriers when updating kernel mappings
  mm/vmalloc: Enter lazy mmu mode while manipulating vmalloc ptes
  arm64/mm: Support huge pte-mapped pages in vmap
  mm/vmalloc: Gracefully unmap huge ptes
  mm/vmalloc: Warn on improper use of vunmap_range()
  arm64/mm: Hoist barriers out of set_ptes_anysz() loop
  ...
parents bbff27b5 217e3cbb

Documentation/ABI/testing/sysfs-devices-system-cpu

+1 −0
Original line number Diff line number Diff line
@@ -544,6 +544,7 @@ What: /sys/devices/system/cpu/cpuX/regs/ 
		/sys/devices/system/cpu/cpuX/regs/identification/

		/sys/devices/system/cpu/cpuX/regs/identification/midr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/revidr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/aidr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/smidr_el1

Date:		June 2016

Contact:	Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>

Documentation/arch/arm64/cpu-feature-registers.rst

+7 −6
Original line number Diff line number Diff line
@@ -72,14 +72,15 @@ there are some issues with their usage. 
    process could be migrated to another CPU by the time it uses the

    register value, unless the CPU affinity is set. Hence, there is no

    guarantee that the value reflects the processor that it is

    currently executing on. The REVIDR is not exposed due to this

    constraint, as REVIDR makes sense only in conjunction with the

    MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs

    at::

    currently executing on. REVIDR and AIDR are not exposed due to this

    constraint, as these registers only make sense in conjunction with

    the MIDR. Alternately, MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are exposed

    via sysfs at::



	/sys/devices/system/cpu/cpu$ID/regs/identification/

	                                              \- midr

	                                              \- revidr

	                                              \- midr_el1

	                                              \- revidr_el1

	                                              \- aidr_el1



3. Implementation

--------------------

Documentation/arch/arm64/sme.rst

+4 −4
Original line number Diff line number Diff line
@@ -69,8 +69,8 @@ model features for SME is included in Appendix A. 
  vectors from 0 to VL/8-1 stored in the same endianness invariant format as is

  used for SVE vectors.



* On thread creation TPIDR2_EL0 is preserved unless CLONE_SETTLS is specified,

  in which case it is set to 0.

* On thread creation PSTATE.ZA and TPIDR2_EL0 are preserved unless CLONE_VM

  is specified, in which case PSTATE.ZA is set to 0 and TPIDR2_EL0 is set to 0.



2.  Vector lengths

------------------
@@ -115,7 +115,7 @@ be zeroed. 
5.  Signal handling

-------------------



* Signal handlers are invoked with streaming mode and ZA disabled.

* Signal handlers are invoked with PSTATE.SM=0, PSTATE.ZA=0, and TPIDR2_EL0=0.



* A new signal frame record TPIDR2_MAGIC is added formatted as a struct

  tpidr2_context to allow access to TPIDR2_EL0 from signal handlers.
@@ -241,7 +241,7 @@ prctl(PR_SME_SET_VL, unsigned long arg) 
      length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag,

      does not constitute a change to the vector length for this purpose.



    * Changing the vector length causes PSTATE.ZA and PSTATE.SM to be cleared.

    * Changing the vector length causes PSTATE.ZA to be cleared.

      Calling PR_SME_SET_VL with vl equal to the thread's current vector

      length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag,

      does not constitute a change to the vector length for this purpose.

arch/arm64/Kconfig

+4 −5
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ config ARM64 
	select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS

	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE

	select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT

	select ARCH_HAS_PREEMPT_LAZY

	select ARCH_HAS_PTDUMP

	select ARCH_HAS_PTE_DEVMAP

	select ARCH_HAS_PTE_SPECIAL
@@ -134,7 +135,6 @@ config ARM64 
	select COMMON_CLK

	select CPU_PM if (SUSPEND || CPU_IDLE)

	select CPUMASK_OFFSTACK if NR_CPUS > 256

	select CRC32

	select DCACHE_WORD_ACCESS

	select DYNAMIC_FTRACE if FUNCTION_TRACER

	select DMA_BOUNCE_UNALIGNED_KMALLOC
@@ -333,9 +333,9 @@ config ARCH_MMAP_RND_BITS_MAX 
	default 24 if ARM64_VA_BITS=39

	default 27 if ARM64_VA_BITS=42

	default 30 if ARM64_VA_BITS=47

	default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES

	default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES

	default 33 if ARM64_VA_BITS=48

	default 29 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_64K_PAGES

	default 31 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_16K_PAGES

	default 33 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52)

	default 14 if ARM64_64K_PAGES

	default 16 if ARM64_16K_PAGES

	default 18
@@ -2285,7 +2285,6 @@ config ARM64_SME 
	bool "ARM Scalable Matrix Extension support"

	default y

	depends on ARM64_SVE

	depends on BROKEN

	help

	  The Scalable Matrix Extension (SME) is an extension to the AArch64

	  execution state which utilises a substantial subset of the SVE

arch/arm64/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ struct cpuinfo_arm64 { 
	u64		reg_dczid;

	u64		reg_midr;

	u64		reg_revidr;

	u64		reg_aidr;

	u64		reg_gmid;

	u64		reg_smidr;

	u64		reg_mpamidr;