Commit 4b19f6b7 authored by Ramalingam C's avatar Ramalingam C Committed by Matt Roper
Browse files

drm/i915/dg2: Add Wa_16013000631 



Invalidate IC cache through pipe control command as part of the ctx
restore flow through indirect ctx pointer.

v2:
 - Move pipe control from xcs indirect context to the rcs indirect
   context.  We'll eventually need this on the CCS engines too, but
   support for those hasn't landed yet.

Cc: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: default avatarRamalingam C <ramalingam.c@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarClint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211116174818.2128062-5-matthew.d.roper@intel.com
parent 34734ab7

drivers/gpu/drm/i915/gt/intel_lrc.c

+5 −0
Original line number Diff line number Diff line
@@ -1167,6 +1167,11 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) 
	cs = gen12_emit_cmd_buf_wa(ce, cs);

	cs = gen12_emit_restore_scratch(ce, cs);



	/* Wa_16013000631:dg2 */

	if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) ||

	    IS_DG2_G11(ce->engine->i915))

		cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0);



	return cs;

}