Commit 512f9f15 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2026-04-02' of https://gitlab.freedesktop.org/drm/msm into drm-next 



Changes for v7.1

CI:
- Uprev mesa
- Restore CI jobs for Qualcomm APQ8016 and APQ8096 devices

Core:
- Switched to of_get_available_child_by_name()

DPU:
- Fixes for DSC panels
- Fixed brownout because of the frequency / OPP mismatch
- Quad pipe preparation (not enabled yet)
- Switched to virtual planes by default
- Dropped VBIF_NRT support
- Added support for Eliza platform
- Reworked alpha handling
- Switched to correct CWB definitions on Eliza
- Dropped dummy INTF_0 on MSM8953
- Corrected INTFs related to DP-MST

DP:
- Removed debug prints looking into PHY internals

DSI:
- Fixes for DSC panels
- RGB101010 support
- Support for SC8280XP
- Moved PHY bindings from display/ to phy/

GPU:
- Preemption support for x2-85 and a840
- IFPC support for a840
- SKU detection support for x2-85 and a840
- Expose AQE support (VK ray-pipeline)
- Avoid locking in VM_BIND fence signaling path
- Fix to avoid reclaim in GPU snapshot path
- Disallow foreign mapping of _NO_SHARE BOs
- Couple a6xx gpu snapshot fixes
- Various other fixes

HDMI:
- Fixed infoframes programming

MDP5:
- Dropped support for MSM8974v1
- Dropped now unused code for MSM8974 v1 and SDM660 / MSM8998

Also misc small fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <rob.clark@oss.qualcomm.com>
Link: https://patch.msgid.link/CACSVV012vn73BaUfk=Hw4WkQHZNPHiqfifWEunAqMc2EGOWUEQ@mail.gmail.com
parents cdd65e8b a972d1b8

Documentation/devicetree/bindings/display/msm/dp-controller.yaml

+1 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ properties: 


      - items:

          - enum:

              - qcom,eliza-dp

              - qcom,sm8750-dp

          - const: qcom,sm8650-dp

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

+5 −0
Original line number Diff line number Diff line
@@ -49,8 +49,13 @@ properties: 
      - items:

          - enum:

              - qcom,qcs8300-dsi-ctrl

              - qcom,sc8280xp-dsi-ctrl

          - const: qcom,sa8775p-dsi-ctrl

          - const: qcom,mdss-dsi-ctrl

      - items:

          - const: qcom,eliza-dsi-ctrl

          - const: qcom,sm8750-dsi-ctrl

          - const: qcom,mdss-dsi-ctrl

      - enum:

          - qcom,dsi-ctrl-6g-qcm2290

          - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible

Documentation/devicetree/bindings/display/msm/gmu.yaml

+1 −0
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ allOf: 
        compatible:

          contains:

            enum:

              - qcom,adreno-gmu-615.0

              - qcom,adreno-gmu-618.0

              - qcom,adreno-gmu-630.2

    then:

Documentation/devicetree/bindings/display/msm/gpu.yaml

+0 −7
Original line number Diff line number Diff line
@@ -440,13 +440,6 @@ allOf: 
        clocks: false

        clock-names: false



        reg-names:

          minItems: 1

          items:

            - const: kgsl_3d0_reg_memory

            - const: cx_mem

            - const: cx_dbgc



examples:

  - |

Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml

0 → 100644
+494 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,eliza-mdss.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Eliza SoC Display MDSS



maintainers:

  - Krzysztof Kozlowski <krzk@kernel.org>



description:

  Eliza SoC Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU

  display controller, DSI and DP interfaces etc.



$ref: /schemas/display/msm/mdss-common.yaml#



properties:

  compatible:

    const: qcom,eliza-mdss



  clocks:

    items:

      - description: Display AHB

      - description: Display hf AXI

      - description: Display core



  iommus:

    maxItems: 1



  interconnects:

    items:

      - description: Interconnect path from mdp0 port to the data bus

      - description: Interconnect path from CPU to the reg bus



  interconnect-names:

    items:

      - const: mdp0-mem

      - const: cpu-cfg



patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        contains:

          const: qcom,eliza-dpu



  "^displayport-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        contains:

          const: qcom,eliza-dp



  "^dsi@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        contains:

          const: qcom,eliza-dsi-ctrl



  "^phy@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        contains:

          const: qcom,eliza-dsi-phy-4nm



required:

  - compatible



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/interconnect/qcom,icc.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/phy/phy-qcom-qmp.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>



    display-subsystem@ae00000 {

        compatible = "qcom,eliza-mdss";

        reg = <0x0ae00000 0x1000>;

        reg-names = "mdss";

        ranges;



        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;



        clocks = <&disp_cc_mdss_ahb_clk>,

                 <&gcc_disp_hf_axi_clk>,

                 <&disp_cc_mdss_mdp_clk>;



        resets = <&disp_cc_mdss_core_bcr>;



        interconnects = <&mmss_noc_master_mdp QCOM_ICC_TAG_ALWAYS

                         &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,

                        <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY

                         &config_noc_slave_display_cfg QCOM_ICC_TAG_ACTIVE_ONLY>;

        interconnect-names = "mdp0-mem",

                             "cpu-cfg";



        power-domains = <&mdss_gdsc>;



        iommus = <&apps_smmu 0x800 0x2>;



        interrupt-controller;

        #interrupt-cells = <1>;



        #address-cells = <1>;

        #size-cells = <1>;



        mdss_mdp: display-controller@ae01000 {

            compatible = "qcom,eliza-dpu";

            reg = <0x0ae01000 0x93000>,

                  <0x0aeb0000 0x2008>;

            reg-names = "mdp",

                        "vbif";



            interrupts-extended = <&mdss 0>;



            clocks = <&gcc_disp_hf_axi_clk>,

                     <&disp_cc_mdss_ahb_clk>,

                     <&disp_cc_mdss_mdp_lut_clk>,

                     <&disp_cc_mdss_mdp_clk>,

                     <&disp_cc_mdss_vsync_clk>;

            clock-names = "nrt_bus",

                          "iface",

                          "lut",

                          "core",

                          "vsync";



            assigned-clocks = <&disp_cc_mdss_vsync_clk>;

            assigned-clock-rates = <19200000>;



            operating-points-v2 = <&mdp_opp_table>;



            power-domains = <&rpmhpd RPMHPD_MMCX>;



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;



                    dpu_intf1_out: endpoint {

                        remote-endpoint = <&mdss_dsi0_in>;

                    };

                };



                port@1 {

                    reg = <1>;



                    dpu_intf2_out: endpoint {

                        remote-endpoint = <&mdss_dsi1_in>;

                    };

                };



                port@2 {

                    reg = <2>;



                    dpu_intf0_out: endpoint {

                        remote-endpoint = <&mdss_dp0_in>;

                    };

                };

            };



            mdp_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-150000000 {

                    opp-hz = /bits/ 64 <150000000>;

                    required-opps = <&rpmhpd_opp_low_svs_d1>;

                };



                opp-207000000 {

                    opp-hz = /bits/ 64 <207000000>;

                    required-opps = <&rpmhpd_opp_low_svs>;

                };



                opp-342000000 {

                    opp-hz = /bits/ 64 <342000000>;

                    required-opps = <&rpmhpd_opp_svs>;

                };



                opp-417000000 {

                    opp-hz = /bits/ 64 <417000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };



                opp-532000000 {

                    opp-hz = /bits/ 64 <532000000>;

                    required-opps = <&rpmhpd_opp_nom>;

                };



                opp-600000000 {

                    opp-hz = /bits/ 64 <600000000>;

                    required-opps = <&rpmhpd_opp_nom_l1>;

                };



                opp-660000000 {

                    opp-hz = /bits/ 64 <660000000>;

                    required-opps = <&rpmhpd_opp_turbo>;

                };

            };

        };



        dsi@ae94000 {

            compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";

            reg = <0x0ae94000 0x400>;

            reg-names = "dsi_ctrl";



            interrupts-extended = <&mdss 4>;



            clocks = <&disp_cc_mdss_byte0_clk>,

                     <&disp_cc_mdss_byte0_intf_clk>,

                     <&disp_cc_mdss_pclk0_clk>,

                     <&disp_cc_mdss_esc0_clk>,

                     <&disp_cc_mdss_ahb_clk>,

                     <&gcc_disp_hf_axi_clk>,

                     <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,

                     <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,

                     <&disp_cc_esync0_clk>,

                     <&disp_cc_osc_clk>,

                     <&disp_cc_mdss_byte0_clk_src>,

                     <&disp_cc_mdss_pclk0_clk_src>;

            clock-names = "byte",

                          "byte_intf",

                          "pixel",

                          "core",

                          "iface",

                          "bus",

                          "dsi_pll_pixel",

                          "dsi_pll_byte",

                          "esync",

                          "osc",

                          "byte_src",

                          "pixel_src";



            operating-points-v2 = <&mdss_dsi_opp_table>;



            power-domains = <&rpmhpd RPMHPD_MMCX>;



            phys = <&mdss_dsi0_phy>;

            phy-names = "dsi";



            #address-cells = <1>;

            #size-cells = <0>;



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;



                    mdss_dsi0_in: endpoint {

                        remote-endpoint = <&dpu_intf1_out>;

                    };

                };



                port@1 {

                    reg = <1>;



                    mdss_dsi0_out: endpoint {

                        remote-endpoint = <&panel0_in>;

                        data-lanes = <0 1 2 3>;

                    };

                };

            };



            mdss_dsi_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-140630000 {

                    opp-hz = /bits/ 64 <140630000>;

                    required-opps = <&rpmhpd_opp_low_svs_d1>;

                };



                opp-187500000 {

                    opp-hz = /bits/ 64 <187500000>;

                    required-opps = <&rpmhpd_opp_low_svs>;

                };



                opp-300000000 {

                    opp-hz = /bits/ 64 <300000000>;

                    required-opps = <&rpmhpd_opp_svs>;

                };



                opp-358000000 {

                    opp-hz = /bits/ 64 <358000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };

            };

        };



        mdss_dsi0_phy: phy@ae95000 {

            compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";

            reg = <0x0ae95000 0x200>,

                  <0x0ae95200 0x280>,

                  <0x0ae95500 0x400>;

            reg-names = "dsi_phy",

                        "dsi_phy_lane",

                        "dsi_pll";



            clocks = <&disp_cc_mdss_ahb_clk>,

                     <&bi_tcxo_div2>;

            clock-names = "iface",

                          "ref";



            #clock-cells = <1>;

            #phy-cells = <0>;



            vdds-supply = <&vreg_l2b>;

        };



        dsi@ae96000 {

            compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";

            reg = <0x0ae96000 0x400>;

            reg-names = "dsi_ctrl";



            interrupts-extended = <&mdss 5>;



            clocks = <&disp_cc_mdss_byte1_clk>,

                     <&disp_cc_mdss_byte1_intf_clk>,

                     <&disp_cc_mdss_pclk1_clk>,

                     <&disp_cc_mdss_esc1_clk>,

                     <&disp_cc_mdss_ahb_clk>,

                     <&gcc_disp_hf_axi_clk>,

                     <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,

                     <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,

                     <&disp_cc_esync1_clk>,

                     <&disp_cc_osc_clk>,

                     <&disp_cc_mdss_byte1_clk_src>,

                     <&disp_cc_mdss_pclk1_clk_src>;

            clock-names = "byte",

                          "byte_intf",

                          "pixel",

                          "core",

                          "iface",

                          "bus",

                          "dsi_pll_pixel",

                          "dsi_pll_byte",

                          "esync",

                          "osc",

                          "byte_src",

                          "pixel_src";



            operating-points-v2 = <&mdss_dsi_opp_table>;



            power-domains = <&rpmhpd RPMHPD_MMCX>;



            phys = <&mdss_dsi1_phy>;

            phy-names = "dsi";



            vdda-supply = <&vreg_l4b>;



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;



                    mdss_dsi1_in: endpoint {

                        remote-endpoint = <&dpu_intf2_out>;

                    };

                };



                port@1 {

                    reg = <1>;



                    mdss_dsi1_out: endpoint {

                        remote-endpoint = <&panel1_in>;

                        data-lanes = <0 1 2 3>;

                    };

                };

            };

        };



        mdss_dsi1_phy: phy@ae97000 {

            compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";

            reg = <0x0ae97000 0x200>,

                  <0x0ae97200 0x280>,

                  <0x0ae97500 0x400>;

            reg-names = "dsi_phy",

                        "dsi_phy_lane",

                        "dsi_pll";



            clocks = <&disp_cc_mdss_ahb_clk>,

                     <&rpmhcc RPMH_CXO_CLK>;

            clock-names = "iface",

                          "ref";



            #clock-cells = <1>;

            #phy-cells = <0>;



            vdds-supply = <&vreg_l2b>;

        };



        displayport-controller@af54000 {

            compatible = "qcom,eliza-dp", "qcom,sm8650-dp";

            reg = <0xaf54000 0x104>,

                  <0xaf54200 0xc0>,

                  <0xaf55000 0x770>,

                  <0xaf56000 0x9c>,

                  <0xaf57000 0x9c>;



            interrupts-extended = <&mdss 12>;



            clocks = <&disp_cc_mdss_ahb_clk>,

                     <&disp_cc_mdss_dptx0_aux_clk>,

                     <&disp_cc_mdss_dptx0_link_clk>,

                     <&disp_cc_mdss_dptx0_link_intf_clk>,

                     <&disp_cc_mdss_dptx0_pixel0_clk>,

                     <&disp_cc_mdss_dptx0_pixel1_clk>;

            clock-names = "core_iface",

                          "core_aux",

                          "ctrl_link",

                          "ctrl_link_iface",

                          "stream_pixel",

                          "stream_1_pixel";



            assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>,

                              <&disp_cc_mdss_dptx0_pixel0_clk_src>,

                              <&disp_cc_mdss_dptx0_pixel1_clk_src>;

            assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,

                                     <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,

                                     <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;



            operating-points-v2 = <&dp_opp_table>;



            power-domains = <&rpmhpd RPMHPD_MMCX>;



            phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;

            phy-names = "dp";



            #sound-dai-cells = <0>;



            dp_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-192000000 {

                    opp-hz = /bits/ 64 <192000000>;

                    required-opps = <&rpmhpd_opp_low_svs_d1>;

                };



                opp-270000000 {

                    opp-hz = /bits/ 64 <270000000>;

                    required-opps = <&rpmhpd_opp_low_svs>;

                };



                opp-540000000 {

                    opp-hz = /bits/ 64 <540000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };



                opp-810000000 {

                    opp-hz = /bits/ 64 <810000000>;

                    required-opps = <&rpmhpd_opp_nom>;

                };

            };



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;



                    mdss_dp0_in: endpoint {

                        remote-endpoint = <&dpu_intf0_out>;

                    };

                };



                port@1 {

                    reg = <1>;



                    mdss_dp0_out: endpoint {

                        data-lanes = <0 1 2 3>;

                        remote-endpoint = <&usb_dp_qmpphy_dp_in>;

                        link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;

                    };

                };

            };

        };

    };