Commit 54020e2b authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Rodrigo Vivi
Browse files

drm/xe: Define registers used by memory based irq processing 



The RING_INT_SRC_RPT_PTR register points to a cacheline in memory
to which an engine must report as source of interrupt prior to
generating an interrupt to the host.

The RING_INT_STATUS_RPT_PTR register points to the first cacheline
of the Interrupt Status Report (ISR) page (4KB) in graphics memory
to which all engines report their interrupt status.

The RING_IMR register has the interrupt enables and interrupt masks
for an engine.

We will refer to these registers shortly.

Bspec: 45963, 45964, 45965
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-3-michal.wajdeczko@intel.com


Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
parent 6901f732

drivers/gpu/drm/xe/regs/xe_engine_regs.h

+2 −0
Original line number Diff line number Diff line
@@ -75,7 +75,9 @@ 
#define FF_THREAD_MODE(base)			XE_REG((base) + 0xa0)

#define   FF_TESSELATION_DOP_GATE_DISABLE	BIT(19)



#define RING_INT_SRC_RPT_PTR(base)		XE_REG((base) + 0xa4)

#define RING_IMR(base)				XE_REG((base) + 0xa8)

#define RING_INT_STATUS_RPT_PTR(base)		XE_REG((base) + 0xac)



#define RING_EIR(base)				XE_REG((base) + 0xb0)

#define RING_EMR(base)				XE_REG((base) + 0xb4)