Commit 5457880b authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/dwc-sophgo' 

- Disable L0s and L1 on Sophgo 2044 PCIe Root Ports (Inochi Amaoto)

* pci/controller/dwc-sophgo:
  PCI: sophgo: Disable L0s and L1 on Sophgo 2044 PCIe Root Ports
parents 42e8a4ef 613f3255

drivers/pci/controller/dwc/pcie-sophgo.c

+18 −0
Original line number Diff line number Diff line
@@ -161,6 +161,22 @@ static void sophgo_pcie_msi_enable(struct dw_pcie_rp *pp) 
	raw_spin_unlock_irqrestore(&pp->lock, flags);

}



static void sophgo_pcie_disable_l0s_l1(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	u32 offset, val;



	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);



	dw_pcie_dbi_ro_wr_en(pci);



	val = dw_pcie_readl_dbi(pci, PCI_EXP_LNKCAP + offset);

	val &= ~(PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1);

	dw_pcie_writel_dbi(pci, PCI_EXP_LNKCAP + offset, val);



	dw_pcie_dbi_ro_wr_dis(pci);

}



static int sophgo_pcie_host_init(struct dw_pcie_rp *pp)

{

	int irq;
@@ -171,6 +187,8 @@ static int sophgo_pcie_host_init(struct dw_pcie_rp *pp) 


	irq_set_chained_handler_and_data(irq, sophgo_pcie_intx_handler, pp);



	sophgo_pcie_disable_l0s_l1(pp);



	sophgo_pcie_msi_enable(pp);



	return 0;