Commit 58bc0f0b authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Jakub Kicinski
Browse files

net: stmmac: arrange register fields after register offsets 



Arrange the register fields to be after their corresponding register
offset definitions, which groups all the definitions for a register
together.

Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vdtwD-00000002Gu0-0nTN@rmk-PC.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 8409495b

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

+68 −69
Original line number Diff line number Diff line
@@ -16,28 +16,22 @@ 
#define DMA_CHANNEL_NB_MAX		1



#define DMA_BUS_MODE			0x00001000

#define DMA_SYS_BUS_MODE		0x00001004

#define DMA_STATUS			0x00001008

#define DMA_DEBUG_STATUS_0		0x0000100c

#define DMA_DEBUG_STATUS_1		0x00001010

#define DMA_DEBUG_STATUS_2		0x00001014

#define DMA_AXI_BUS_MODE		0x00001028

#define DMA_TBS_CTRL			0x00001050



/* DMA Bus Mode bitmap */

#define DMA_BUS_MODE_DCHE		BIT(19)

#define DMA_BUS_MODE_INTM_MASK		GENMASK(17, 16)

#define DMA_BUS_MODE_INTM_MODE1		0x1

#define DMA_BUS_MODE_SFT_RESET		BIT(0)



/* DMA SYS Bus Mode bitmap */

#define DMA_SYS_BUS_MODE		0x00001004



#define DMA_BUS_MODE_SPH		BIT(24)

#define DMA_BUS_MODE_PBL		BIT(16)

#define DMA_BUS_MODE_RPBL_MASK		GENMASK(21, 16)

#define DMA_BUS_MODE_MB			BIT(14)

#define DMA_BUS_MODE_FB			BIT(0)



/* DMA Interrupt top status */

#define DMA_STATUS			0x00001008



#define DMA_STATUS_MAC			BIT(17)

#define DMA_STATUS_MTL			BIT(16)

#define DMA_STATUS_CHAN7		BIT(7)
@@ -49,11 +43,15 @@ 
#define DMA_STATUS_CHAN1		BIT(1)

#define DMA_STATUS_CHAN0		BIT(0)



/* DMA debug status bitmap */

#define DMA_DEBUG_STATUS_0		0x0000100c

#define DMA_DEBUG_STATUS_1		0x00001010

#define DMA_DEBUG_STATUS_2		0x00001014



#define DMA_DEBUG_STATUS_TS_MASK	0xf

#define DMA_DEBUG_STATUS_RS_MASK	0xf



/* DMA AXI bitmap */

#define DMA_AXI_BUS_MODE		0x00001028



#define DMA_AXI_EN_LPI			BIT(31)

#define DMA_AXI_LPI_XIT_FRM		BIT(30)

#define DMA_AXI_WR_OSR_LMT		GENMASK(27, 24)
@@ -70,7 +68,8 @@ 
					DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \

					DMA_AXI_BLEN4)



/* DMA TBS Control */

#define DMA_TBS_CTRL			0x00001050



#define DMA_TBS_FTOS			GENMASK(31, 8)

#define DMA_TBS_FTOV			BIT(0)

#define DMA_TBS_DEF_FTOS		(DMA_TBS_FTOS | DMA_TBS_FTOV)
@@ -95,8 +94,22 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs, 
#define DMA_CHAN_REG_NUMBER		17



#define DMA_CHAN_CONTROL(addrs, x)	dma_chanx_base_addr(addrs, x)



#define DMA_CONTROL_SPH			BIT(24)

#define DMA_CONTROL_MSS_MASK		GENMASK(13, 0)



#define DMA_CHAN_TX_CONTROL(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x4)



#define DMA_CONTROL_EDSE		BIT(28)

#define DMA_CONTROL_TSE			BIT(12)

#define DMA_CONTROL_OSP			BIT(4)

#define DMA_CONTROL_ST			BIT(0)



#define DMA_CHAN_RX_CONTROL(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x8)



#define DMA_CONTROL_SR			BIT(0)

#define DMA_RBSZ_MASK			GENMASK(14, 1)



#define DMA_CHAN_TX_BASE_ADDR_HI(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x10)

#define DMA_CHAN_TX_BASE_ADDR(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x14)

#define DMA_CHAN_RX_BASE_ADDR_HI(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x18)
@@ -105,7 +118,49 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs, 
#define DMA_CHAN_RX_END_ADDR(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x28)

#define DMA_CHAN_TX_RING_LEN(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x2c)

#define DMA_CHAN_RX_RING_LEN(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x30)



#define DMA_CHAN_INTR_ENA(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x34)



#define DMA_CHAN_INTR_ENA_NIE		BIT(16)

#define DMA_CHAN_INTR_ENA_AIE		BIT(15)

#define DMA_CHAN_INTR_ENA_NIE_4_10	BIT(15)

#define DMA_CHAN_INTR_ENA_AIE_4_10	BIT(14)

#define DMA_CHAN_INTR_ENA_CDE		BIT(13)

#define DMA_CHAN_INTR_ENA_FBE		BIT(12)

#define DMA_CHAN_INTR_ENA_ERE		BIT(11)

#define DMA_CHAN_INTR_ENA_ETE		BIT(10)

#define DMA_CHAN_INTR_ENA_RWE		BIT(9)

#define DMA_CHAN_INTR_ENA_RSE		BIT(8)

#define DMA_CHAN_INTR_ENA_RBUE		BIT(7)

#define DMA_CHAN_INTR_ENA_RIE		BIT(6)

#define DMA_CHAN_INTR_ENA_TBUE		BIT(2)

#define DMA_CHAN_INTR_ENA_TSE		BIT(1)

#define DMA_CHAN_INTR_ENA_TIE		BIT(0)



#define DMA_CHAN_INTR_NORMAL		(DMA_CHAN_INTR_ENA_NIE | \

					 DMA_CHAN_INTR_ENA_RIE | \

					 DMA_CHAN_INTR_ENA_TIE)



#define DMA_CHAN_INTR_ABNORMAL		(DMA_CHAN_INTR_ENA_AIE | \

					 DMA_CHAN_INTR_ENA_FBE)

/* DMA default interrupt mask for 4.00 */

#define DMA_CHAN_INTR_DEFAULT_MASK	(DMA_CHAN_INTR_NORMAL | \

					 DMA_CHAN_INTR_ABNORMAL)

#define DMA_CHAN_INTR_DEFAULT_RX	(DMA_CHAN_INTR_ENA_RIE)

#define DMA_CHAN_INTR_DEFAULT_TX	(DMA_CHAN_INTR_ENA_TIE)



#define DMA_CHAN_INTR_NORMAL_4_10	(DMA_CHAN_INTR_ENA_NIE_4_10 | \

					 DMA_CHAN_INTR_ENA_RIE | \

					 DMA_CHAN_INTR_ENA_TIE)



#define DMA_CHAN_INTR_ABNORMAL_4_10	(DMA_CHAN_INTR_ENA_AIE_4_10 | \

					 DMA_CHAN_INTR_ENA_FBE)

/* DMA default interrupt mask for 4.10a */

#define DMA_CHAN_INTR_DEFAULT_MASK_4_10	(DMA_CHAN_INTR_NORMAL_4_10 | \

					 DMA_CHAN_INTR_ABNORMAL_4_10)

#define DMA_CHAN_INTR_DEFAULT_RX_4_10	(DMA_CHAN_INTR_ENA_RIE)

#define DMA_CHAN_INTR_DEFAULT_TX_4_10	(DMA_CHAN_INTR_ENA_TIE)



#define DMA_CHAN_RX_WATCHDOG(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x38)

#define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x3c)

#define DMA_CHAN_CUR_TX_DESC(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x44)
@@ -116,20 +171,6 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs, 
#define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x5c)

#define DMA_CHAN_STATUS(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x60)



/* DMA Control X */

#define DMA_CONTROL_SPH			BIT(24)

#define DMA_CONTROL_MSS_MASK		GENMASK(13, 0)



/* DMA Tx Channel X Control register defines */

#define DMA_CONTROL_EDSE		BIT(28)

#define DMA_CONTROL_TSE			BIT(12)

#define DMA_CONTROL_OSP			BIT(4)

#define DMA_CONTROL_ST			BIT(0)



/* DMA Rx Channel X Control register defines */

#define DMA_CONTROL_SR			BIT(0)

#define DMA_RBSZ_MASK			GENMASK(14, 1)



/* Interrupt status per channel */

#define DMA_CHAN_STATUS_REB		GENMASK(21, 19)

#define DMA_CHAN_STATUS_REB_SHIFT	19
@@ -168,48 +209,6 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs, 
					 DMA_CHAN_STATUS_TI | \

					 DMA_CHAN_STATUS_MSK_COMMON)



/* Interrupt enable bits per channel */

#define DMA_CHAN_INTR_ENA_NIE		BIT(16)

#define DMA_CHAN_INTR_ENA_AIE		BIT(15)

#define DMA_CHAN_INTR_ENA_NIE_4_10	BIT(15)

#define DMA_CHAN_INTR_ENA_AIE_4_10	BIT(14)

#define DMA_CHAN_INTR_ENA_CDE		BIT(13)

#define DMA_CHAN_INTR_ENA_FBE		BIT(12)

#define DMA_CHAN_INTR_ENA_ERE		BIT(11)

#define DMA_CHAN_INTR_ENA_ETE		BIT(10)

#define DMA_CHAN_INTR_ENA_RWE		BIT(9)

#define DMA_CHAN_INTR_ENA_RSE		BIT(8)

#define DMA_CHAN_INTR_ENA_RBUE		BIT(7)

#define DMA_CHAN_INTR_ENA_RIE		BIT(6)

#define DMA_CHAN_INTR_ENA_TBUE		BIT(2)

#define DMA_CHAN_INTR_ENA_TSE		BIT(1)

#define DMA_CHAN_INTR_ENA_TIE		BIT(0)



#define DMA_CHAN_INTR_NORMAL		(DMA_CHAN_INTR_ENA_NIE | \

					 DMA_CHAN_INTR_ENA_RIE | \

					 DMA_CHAN_INTR_ENA_TIE)



#define DMA_CHAN_INTR_ABNORMAL		(DMA_CHAN_INTR_ENA_AIE | \

					 DMA_CHAN_INTR_ENA_FBE)

/* DMA default interrupt mask for 4.00 */

#define DMA_CHAN_INTR_DEFAULT_MASK	(DMA_CHAN_INTR_NORMAL | \

					 DMA_CHAN_INTR_ABNORMAL)

#define DMA_CHAN_INTR_DEFAULT_RX	(DMA_CHAN_INTR_ENA_RIE)

#define DMA_CHAN_INTR_DEFAULT_TX	(DMA_CHAN_INTR_ENA_TIE)



#define DMA_CHAN_INTR_NORMAL_4_10	(DMA_CHAN_INTR_ENA_NIE_4_10 | \

					 DMA_CHAN_INTR_ENA_RIE | \

					 DMA_CHAN_INTR_ENA_TIE)



#define DMA_CHAN_INTR_ABNORMAL_4_10	(DMA_CHAN_INTR_ENA_AIE_4_10 | \

					 DMA_CHAN_INTR_ENA_FBE)

/* DMA default interrupt mask for 4.10a */

#define DMA_CHAN_INTR_DEFAULT_MASK_4_10	(DMA_CHAN_INTR_NORMAL_4_10 | \

					 DMA_CHAN_INTR_ABNORMAL_4_10)

#define DMA_CHAN_INTR_DEFAULT_RX_4_10	(DMA_CHAN_INTR_ENA_RIE)

#define DMA_CHAN_INTR_DEFAULT_TX_4_10	(DMA_CHAN_INTR_ENA_TIE)



/* channel 0 specific fields */

#define DMA_CHAN0_DBG_STAT_TPS		GENMASK(15, 12)

#define DMA_CHAN0_DBG_STAT_TPS_SHIFT	12

#define DMA_CHAN0_DBG_STAT_RPS		GENMASK(11, 8)

drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h

+86 −83
Original line number Diff line number Diff line
@@ -13,13 +13,99 @@ 


/* DMA CRS Control and Status Register Mapping */

#define DMA_BUS_MODE		0x00001000	/* Bus Mode */



#define DMA_BUS_MODE_SFT_RESET	0x00000001	/* Software Reset */



#define DMA_XMT_POLL_DEMAND	0x00001004	/* Transmit Poll Demand */

#define DMA_RCV_POLL_DEMAND	0x00001008	/* Received Poll Demand */

#define DMA_RCV_BASE_ADDR	0x0000100c	/* Receive List Base */

#define DMA_TX_BASE_ADDR	0x00001010	/* Transmit List Base */



#define DMA_STATUS		0x00001014	/* Status Register */

#define DMA_STATUS_GLPII	0x40000000	/* GMAC LPI interrupt */

#define DMA_STATUS_GPI		0x10000000	/* PMT interrupt */

#define DMA_STATUS_GMI		0x08000000	/* MMC interrupt */

#define DMA_STATUS_GLI		0x04000000	/* GMAC Line interface int */

#define DMA_STATUS_EB_MASK	0x00380000	/* Error Bits Mask */

#define DMA_STATUS_EB_TX_ABORT	0x00080000	/* Error Bits - TX Abort */

#define DMA_STATUS_EB_RX_ABORT	0x00100000	/* Error Bits - RX Abort */

#define DMA_STATUS_TS_MASK	GENMASK(22, 20)	/* Transmit Process State */

#define DMA_STATUS_RS_MASK	GENMASK(19, 17)	/* Receive Process State */

#define DMA_STATUS_NIS	0x00010000	/* Normal Interrupt Summary */

#define DMA_STATUS_AIS	0x00008000	/* Abnormal Interrupt Summary */

#define DMA_STATUS_ERI	0x00004000	/* Early Receive Interrupt */

#define DMA_STATUS_FBI	0x00002000	/* Fatal Bus Error Interrupt */

#define DMA_STATUS_ETI	0x00000400	/* Early Transmit Interrupt */

#define DMA_STATUS_RWT	0x00000200	/* Receive Watchdog Timeout */

#define DMA_STATUS_RPS	0x00000100	/* Receive Process Stopped */

#define DMA_STATUS_RU	0x00000080	/* Receive Buffer Unavailable */

#define DMA_STATUS_RI	0x00000040	/* Receive Interrupt */

#define DMA_STATUS_UNF	0x00000020	/* Transmit Underflow */

#define DMA_STATUS_OVF	0x00000010	/* Receive Overflow */

#define DMA_STATUS_TJT	0x00000008	/* Transmit Jabber Timeout */

#define DMA_STATUS_TU	0x00000004	/* Transmit Buffer Unavailable */

#define DMA_STATUS_TPS	0x00000002	/* Transmit Process Stopped */

#define DMA_STATUS_TI	0x00000001	/* Transmit Interrupt */



#define DMA_STATUS_MSK_COMMON		(DMA_STATUS_NIS | \

					 DMA_STATUS_AIS | \

					 DMA_STATUS_FBI)



#define DMA_STATUS_MSK_RX		(DMA_STATUS_ERI | \

					 DMA_STATUS_RWT | \

					 DMA_STATUS_RPS | \

					 DMA_STATUS_RU | \

					 DMA_STATUS_RI | \

					 DMA_STATUS_OVF | \

					 DMA_STATUS_MSK_COMMON)



#define DMA_STATUS_MSK_TX		(DMA_STATUS_ETI | \

					 DMA_STATUS_UNF | \

					 DMA_STATUS_TJT | \

					 DMA_STATUS_TU | \

					 DMA_STATUS_TPS | \

					 DMA_STATUS_TI | \

					 DMA_STATUS_MSK_COMMON)



#define DMA_CONTROL		0x00001018	/* Ctrl (Operational Mode) */



/* DMA Control register defines */

#define DMA_CONTROL_FTF		0x00100000	/* Flush transmit FIFO */

#define DMA_CONTROL_ST		0x00002000	/* Start/Stop Transmission */

#define DMA_CONTROL_SR		0x00000002	/* Start/Stop Receive */



#define DMA_INTR_ENA		0x0000101c	/* Interrupt Enable */



/* DMA Normal interrupt */

#define DMA_INTR_ENA_NIE 0x00010000	/* Normal Summary */

#define DMA_INTR_ENA_TIE 0x00000001	/* Transmit Interrupt */

#define DMA_INTR_ENA_TUE 0x00000004	/* Transmit Buffer Unavailable */

#define DMA_INTR_ENA_RIE 0x00000040	/* Receive Interrupt */

#define DMA_INTR_ENA_ERE 0x00004000	/* Early Receive */



#define DMA_INTR_NORMAL	(DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \

			DMA_INTR_ENA_TIE)



/* DMA Abnormal interrupt */

#define DMA_INTR_ENA_AIE 0x00008000	/* Abnormal Summary */

#define DMA_INTR_ENA_FBE 0x00002000	/* Fatal Bus Error */

#define DMA_INTR_ENA_ETE 0x00000400	/* Early Transmit */

#define DMA_INTR_ENA_RWE 0x00000200	/* Receive Watchdog */

#define DMA_INTR_ENA_RSE 0x00000100	/* Receive Stopped */

#define DMA_INTR_ENA_RUE 0x00000080	/* Receive Buffer Unavailable */

#define DMA_INTR_ENA_UNE 0x00000020	/* Tx Underflow */

#define DMA_INTR_ENA_OVE 0x00000010	/* Receive Overflow */

#define DMA_INTR_ENA_TJE 0x00000008	/* Transmit Jabber */

#define DMA_INTR_ENA_TSE 0x00000002	/* Transmit Stopped */



#define DMA_INTR_ABNORMAL	(DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \

				DMA_INTR_ENA_UNE)



/* DMA default interrupt mask */

#define DMA_INTR_DEFAULT_MASK	(DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)

#define DMA_INTR_DEFAULT_RX	(DMA_INTR_ENA_RIE)

#define DMA_INTR_DEFAULT_TX	(DMA_INTR_ENA_TIE)



#define DMA_MISSED_FRAME_CTR	0x00001020	/* Missed Frame Counter */



/* Following DMA defines are channels oriented */
@@ -47,8 +133,6 @@ static inline u32 dma_chan_base_addr(u32 base, u32 chan) 
#define DMA_CHAN_RX_WATCHDOG(chan)	\

				dma_chan_base_addr(DMA_RX_WATCHDOG, chan)



/* SW Reset */

#define DMA_BUS_MODE_SFT_RESET	0x00000001	/* Software Reset */



/* Rx watchdog register */

#define DMA_RX_WATCHDOG		0x00001024
@@ -77,87 +161,6 @@ static inline u32 dma_chan_base_addr(u32 base, u32 chan) 
#define DMA_CUR_RX_BUF_ADDR	0x00001054	/* Current Host Rx Buffer */

#define DMA_HW_FEATURE		0x00001058	/* HW Feature Register */



/* DMA Control register defines */

#define DMA_CONTROL_ST		0x00002000	/* Start/Stop Transmission */

#define DMA_CONTROL_SR		0x00000002	/* Start/Stop Receive */



/* DMA Normal interrupt */

#define DMA_INTR_ENA_NIE 0x00010000	/* Normal Summary */

#define DMA_INTR_ENA_TIE 0x00000001	/* Transmit Interrupt */

#define DMA_INTR_ENA_TUE 0x00000004	/* Transmit Buffer Unavailable */

#define DMA_INTR_ENA_RIE 0x00000040	/* Receive Interrupt */

#define DMA_INTR_ENA_ERE 0x00004000	/* Early Receive */



#define DMA_INTR_NORMAL	(DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \

			DMA_INTR_ENA_TIE)



/* DMA Abnormal interrupt */

#define DMA_INTR_ENA_AIE 0x00008000	/* Abnormal Summary */

#define DMA_INTR_ENA_FBE 0x00002000	/* Fatal Bus Error */

#define DMA_INTR_ENA_ETE 0x00000400	/* Early Transmit */

#define DMA_INTR_ENA_RWE 0x00000200	/* Receive Watchdog */

#define DMA_INTR_ENA_RSE 0x00000100	/* Receive Stopped */

#define DMA_INTR_ENA_RUE 0x00000080	/* Receive Buffer Unavailable */

#define DMA_INTR_ENA_UNE 0x00000020	/* Tx Underflow */

#define DMA_INTR_ENA_OVE 0x00000010	/* Receive Overflow */

#define DMA_INTR_ENA_TJE 0x00000008	/* Transmit Jabber */

#define DMA_INTR_ENA_TSE 0x00000002	/* Transmit Stopped */



#define DMA_INTR_ABNORMAL	(DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \

				DMA_INTR_ENA_UNE)



/* DMA default interrupt mask */

#define DMA_INTR_DEFAULT_MASK	(DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)

#define DMA_INTR_DEFAULT_RX	(DMA_INTR_ENA_RIE)

#define DMA_INTR_DEFAULT_TX	(DMA_INTR_ENA_TIE)



/* DMA Status register defines */

#define DMA_STATUS_GLPII	0x40000000	/* GMAC LPI interrupt */

#define DMA_STATUS_GPI		0x10000000	/* PMT interrupt */

#define DMA_STATUS_GMI		0x08000000	/* MMC interrupt */

#define DMA_STATUS_GLI		0x04000000	/* GMAC Line interface int */

#define DMA_STATUS_EB_MASK	0x00380000	/* Error Bits Mask */

#define DMA_STATUS_EB_TX_ABORT	0x00080000	/* Error Bits - TX Abort */

#define DMA_STATUS_EB_RX_ABORT	0x00100000	/* Error Bits - RX Abort */

#define DMA_STATUS_TS_MASK	GENMASK(22, 20)	/* Transmit Process State */

#define DMA_STATUS_RS_MASK	GENMASK(19, 17)	/* Receive Process State */

#define DMA_STATUS_NIS	0x00010000	/* Normal Interrupt Summary */

#define DMA_STATUS_AIS	0x00008000	/* Abnormal Interrupt Summary */

#define DMA_STATUS_ERI	0x00004000	/* Early Receive Interrupt */

#define DMA_STATUS_FBI	0x00002000	/* Fatal Bus Error Interrupt */

#define DMA_STATUS_ETI	0x00000400	/* Early Transmit Interrupt */

#define DMA_STATUS_RWT	0x00000200	/* Receive Watchdog Timeout */

#define DMA_STATUS_RPS	0x00000100	/* Receive Process Stopped */

#define DMA_STATUS_RU	0x00000080	/* Receive Buffer Unavailable */

#define DMA_STATUS_RI	0x00000040	/* Receive Interrupt */

#define DMA_STATUS_UNF	0x00000020	/* Transmit Underflow */

#define DMA_STATUS_OVF	0x00000010	/* Receive Overflow */

#define DMA_STATUS_TJT	0x00000008	/* Transmit Jabber Timeout */

#define DMA_STATUS_TU	0x00000004	/* Transmit Buffer Unavailable */

#define DMA_STATUS_TPS	0x00000002	/* Transmit Process Stopped */

#define DMA_STATUS_TI	0x00000001	/* Transmit Interrupt */

#define DMA_CONTROL_FTF		0x00100000	/* Flush transmit FIFO */



#define DMA_STATUS_MSK_COMMON		(DMA_STATUS_NIS | \

					 DMA_STATUS_AIS | \

					 DMA_STATUS_FBI)



#define DMA_STATUS_MSK_RX		(DMA_STATUS_ERI | \

					 DMA_STATUS_RWT | \

					 DMA_STATUS_RPS | \

					 DMA_STATUS_RU | \

					 DMA_STATUS_RI | \

					 DMA_STATUS_OVF | \

					 DMA_STATUS_MSK_COMMON)



#define DMA_STATUS_MSK_TX		(DMA_STATUS_ETI | \

					 DMA_STATUS_UNF | \

					 DMA_STATUS_TJT | \

					 DMA_STATUS_TU | \

					 DMA_STATUS_TPS | \

					 DMA_STATUS_TI | \

					 DMA_STATUS_MSK_COMMON)



#define NUM_DWMAC100_DMA_REGS	9

#define NUM_DWMAC1000_DMA_REGS	23

#define NUM_DWMAC4_DMA_REGS	27