Commit 5a213086 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Eliminate IS_MTL_GRAPHICS_STEP 



Several workarounds are guarded by IS_MTL_GRAPHICS_STEP.  However none
of these workarounds are actually tied to MTL as a platform; they only
relate to the Xe_LPG graphics IP, regardless of what platform it appears
in.  At the moment MTL is the only platform that uses Xe_LPG with IP
versions 12.70 and 12.71, but we can't count on this being true in the
future.  Switch these to use a new IS_GFX_GT_IP_STEP() macro instead
that is purely based on IP version.  IS_GFX_GT_IP_STEP() is also
GT-based rather than device-based, which will help prevent mistakes
where we accidentally try to apply Xe_LPG graphics workarounds to the
Xe_LPM+ media GT and vice-versa.

v2:
 - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be
   used for both graphics and media IP (and any other kind of GTs that
   show up in the future).
v3:
 - Switch back to long-form IS_GFX_GT_IP_STEP macro.  (Jani)
 - Move macro to intel_gt.h.  (Andi)
v4:
 - Build IS_GFX_GT_IP_STEP on top of IS_GFX_GT_IP_RANGE and
   IS_GRAPHICS_STEP building blocks and name the parameters from/until
   rather than begin/fixed.  (Jani)
 - Fix usage examples in comment.
v5:
 - Tweak comment on macro.  (Gustavo)

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-15-matthew.d.roper@intel.com
parent f7696ded

drivers/gpu/drm/i915/display/skl_universal_plane.c

+3 −2
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#include "skl_scaler.h"

#include "skl_universal_plane.h"

#include "skl_watermark.h"

#include "gt/intel_gt.h"

#include "pxp/intel_pxp.h"



static const u32 skl_plane_formats[] = {
@@ -2169,8 +2170,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, 
				 enum pipe pipe, enum plane_id plane_id)

{

	/* Wa_14017240301 */

	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||

	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))

	if (IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||

	    IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))

		return false;



	/* Wa_22011186057 */

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+6 −5
Original line number Diff line number Diff line
@@ -4,9 +4,9 @@ 
 */



#include "gen8_engine_cs.h"

#include "i915_drv.h"

#include "intel_engine_regs.h"

#include "intel_gpu_commands.h"

#include "intel_gt.h"

#include "intel_lrc.h"

#include "intel_ring.h"
@@ -226,8 +226,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs) 
static int mtl_dummy_pipe_control(struct i915_request *rq)

{

	/* Wa_14016712196 */

	if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||

	    IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {

	if (IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||

	    IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {

		u32 *cs;



		/* dummy PIPE_CONTROL + depth flush */
@@ -799,6 +799,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs) 
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

{

	struct drm_i915_private *i915 = rq->i915;

	struct intel_gt *gt = rq->engine->gt;

	u32 flags = (PIPE_CONTROL_CS_STALL |

		     PIPE_CONTROL_TLB_INVALIDATE |

		     PIPE_CONTROL_TILE_CACHE_FLUSH |
@@ -809,8 +810,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 
		     PIPE_CONTROL_FLUSH_ENABLE);



	/* Wa_14016712196 */

	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||

	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))

	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||

	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))

		/* dummy PIPE_CONTROL + depth flush */

		cs = gen12_emit_pipe_control(cs, 0,

					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);

drivers/gpu/drm/i915/gt/intel_gt.h

+20 −0
Original line number Diff line number Diff line
@@ -25,6 +25,26 @@ struct drm_printer; 
	 GRAPHICS_VER_FULL((gt)->i915) >= (from) && \

	 GRAPHICS_VER_FULL((gt)->i915) <= (until)))



/*

 * Check that the GT is a graphics GT with a specific IP version and has

 * a stepping in the range [from, until).  The lower stepping bound is

 * inclusive, the upper bound is exclusive.  The most common use-case of this

 * macro is for checking bounds for workarounds, which usually have a stepping

 * ("from") at which the hardware issue is first present and another stepping

 * ("until") at which a hardware fix is present and the software workaround is

 * no longer necessary.  E.g.,

 *

 *    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)

 *    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B1, STEP_FOREVER)

 *

 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper

 * stepping bound for the specified IP version.

 */

#define IS_GFX_GT_IP_STEP(gt, ipver, from, until) ( \

	BUILD_BUG_ON_ZERO((until) <= (from)) + \

	(IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \

	 IS_GRAPHICS_STEP((gt)->i915, (from), (until))))



#define GT_TRACE(gt, fmt, ...) do {					\

	const struct intel_gt *gt__ __maybe_unused = (gt);		\

	GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev),		\

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

+3 −4
Original line number Diff line number Diff line
@@ -3,8 +3,7 @@ 
 * Copyright © 2022 Intel Corporation

 */



#include "i915_drv.h"



#include "intel_gt.h"

#include "intel_gt_mcr.h"

#include "intel_gt_print.h"

#include "intel_gt_regs.h"
@@ -166,8 +165,8 @@ void intel_gt_mcr_init(struct intel_gt *gt) 
		gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;

	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {

		/* Wa_14016747170 */

		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||

		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))

		if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||

		    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))

			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,

					     intel_uncore_read(gt->uncore,

							       MTL_GT_ACTIVITY_FACTOR));

drivers/gpu/drm/i915/gt/intel_lrc.c

+2 −2
Original line number Diff line number Diff line
@@ -1346,8 +1346,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) 
	cs = gen12_emit_aux_table_inv(ce->engine, cs);



	/* Wa_16014892111 */

	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||

	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||

	if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||

	    IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||

	    IS_DG2(ce->engine->i915))

		cs = dg2_emit_draw_watermark_setting(cs);