Commit 5c8bd7f2 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/j721e' 

- Add PCIe support for J722S SoC (Siddharth Vadapalli)

- Delay PCIE_T_PVPERL_MS (100 ms), not just PCIE_T_PERST_CLK_US (100 us),
  before deasserting PERST# to ensure power and refclk are stable
  (Siddharth Vadapalli)

* pci/controller/j721e:
  PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds
  PCI: j721e: Add PCIe support for J722S SoC
parents 7b86e0a5 22a91204

drivers/pci/controller/cadence/pci-j721e.c

+23 −14
Original line number Diff line number Diff line
@@ -386,6 +386,13 @@ static const struct j721e_pcie_data j784s4_pcie_ep_data = { 
	.max_lanes = 4,

};



static const struct j721e_pcie_data j722s_pcie_rc_data = {

	.mode = PCI_MODE_RC,

	.linkdown_irq_regfield = J7200_LINK_DOWN,

	.byte_access_allowed = true,

	.max_lanes = 1,

};



static const struct of_device_id of_j721e_pcie_match[] = {

	{

		.compatible = "ti,j721e-pcie-host",
@@ -419,6 +426,10 @@ static const struct of_device_id of_j721e_pcie_match[] = { 
		.compatible = "ti,j784s4-pcie-ep",

		.data = &j784s4_pcie_ep_data,

	},

	{

		.compatible = "ti,j722s-pcie-host",

		.data = &j722s_pcie_rc_data,

	},

	{},

};
@@ -572,15 +583,14 @@ static int j721e_pcie_probe(struct platform_device *pdev) 
		pcie->refclk = clk;



		/*

		 * The "Power Sequencing and Reset Signal Timings" table of the

		 * PCI Express Card Electromechanical Specification, Revision

		 * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#

		 * should be deasserted after minimum of 100us once REFCLK is

		 * stable. The REFCLK to the connector in RC mode is selected

		 * while enabling the PHY. So deassert PERST# after 100 us.

		 * Section 2.2 of the PCI Express Card Electromechanical

		 * Specification (Revision 5.1) mandates that the deassertion

		 * of the PERST# signal should be delayed by 100 ms (TPVPERL).

		 * This shall ensure that the power and the reference clock

		 * are stable.

		 */

		if (gpiod) {

			fsleep(PCIE_T_PERST_CLK_US);

			msleep(PCIE_T_PVPERL_MS);

			gpiod_set_value_cansleep(gpiod, 1);

		}
@@ -671,15 +681,14 @@ static int j721e_pcie_resume_noirq(struct device *dev) 
			return ret;



		/*

		 * The "Power Sequencing and Reset Signal Timings" table of the

		 * PCI Express Card Electromechanical Specification, Revision

		 * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#

		 * should be deasserted after minimum of 100us once REFCLK is

		 * stable. The REFCLK to the connector in RC mode is selected

		 * while enabling the PHY. So deassert PERST# after 100 us.

		 * Section 2.2 of the PCI Express Card Electromechanical

		 * Specification (Revision 5.1) mandates that the deassertion

		 * of the PERST# signal should be delayed by 100 ms (TPVPERL).

		 * This shall ensure that the power and the reference clock

		 * are stable.

		 */

		if (pcie->reset_gpio) {

			fsleep(PCIE_T_PERST_CLK_US);

			msleep(PCIE_T_PVPERL_MS);

			gpiod_set_value_cansleep(pcie->reset_gpio, 1);

		}