Commit 62589808 authored by Jesse Brandeburg's avatar Jesse Brandeburg Committed by Tony Nguyen
Browse files

i40e: field get conversion 



Refactor the i40e driver to use FIELD_GET() for mask and shift reads,
which reduces lines of code and adds clarity of intent.

This code was generated by the following coccinelle/spatch script and
then manually repaired.

While making one of the conversions, an if() check was inverted to
return early and avoid un-necessary indentation of the remainder of the
function. In some other cases a stack variable was moved inside the
block where it was used while doing cleanups/review.

A couple places were changed to use le16_get_bits() instead of FIELD_GET
with a le16_to_cpu combination.

@get@
constant shift,mask;
metavariable type T;
expression a;
@@
-(((T)(a) & mask) >> shift)
+FIELD_GET(mask, a)

and applied via:
spatch --sp-file field_prep.cocci --in-place --dir \
 drivers/net/ethernet/intel/

Cc: Julia Lawall <Julia.Lawall@inria.fr>
Reviewed-by: default avatarAleksandr Loktionov <aleksandr.loktionov@intel.com>
Reviewed-by: default avatarMarcin Szycik <marcin.szycik@linux.intel.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Signed-off-by: default avatarJesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent a8e0c7a6

drivers/net/ethernet/intel/i40e/i40e_common.c

+21 −35
Original line number Diff line number Diff line
@@ -664,11 +664,11 @@ int i40e_init_shared_code(struct i40e_hw *hw) 
	hw->phy.get_link_info = true;



	/* Determine port number and PF number*/

	port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)

					   >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;

	port = FIELD_GET(I40E_PFGEN_PORTNUM_PORT_NUM_MASK,

			 rd32(hw, I40E_PFGEN_PORTNUM));

	hw->port = (u8)port;

	ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>

						 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;

	ari = FIELD_GET(I40E_GLPCI_CAPSUP_ARI_EN_MASK,

			rd32(hw, I40E_GLPCI_CAPSUP));

	func_rid = rd32(hw, I40E_PF_FUNC_RID);

	if (ari)

		hw->pf_id = (u8)(func_rid & 0xff);
@@ -986,9 +986,8 @@ int i40e_pf_reset(struct i40e_hw *hw) 
	 * The grst delay value is in 100ms units, and we'll wait a

	 * couple counts longer to be sure we don't just miss the end.

	 */

	grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &

		    I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>

		    I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;

	grst_del = FIELD_GET(I40E_GLGEN_RSTCTL_GRSTDEL_MASK,

			     rd32(hw, I40E_GLGEN_RSTCTL));



	/* It can take upto 15 secs for GRST steady state.

	 * Bump it to 16 secs max to be safe.
@@ -1080,26 +1079,20 @@ void i40e_clear_hw(struct i40e_hw *hw) 


	/* get number of interrupts, queues, and VFs */

	val = rd32(hw, I40E_GLPCI_CNF2);

	num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>

		     I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;

	num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>

		     I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;

	num_pf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_PF_N_MASK, val);

	num_vf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_VF_N_MASK, val);



	val = rd32(hw, I40E_PFLAN_QALLOC);

	base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>

		     I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;

	j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>

	    I40E_PFLAN_QALLOC_LASTQ_SHIFT;

	base_queue = FIELD_GET(I40E_PFLAN_QALLOC_FIRSTQ_MASK, val);

	j = FIELD_GET(I40E_PFLAN_QALLOC_LASTQ_MASK, val);

	if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue)

		num_queues = (j - base_queue) + 1;

	else

		num_queues = 0;



	val = rd32(hw, I40E_PF_VT_PFALLOC);

	i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>

	    I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;

	j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>

	    I40E_PF_VT_PFALLOC_LASTVF_SHIFT;

	i = FIELD_GET(I40E_PF_VT_PFALLOC_FIRSTVF_MASK, val);

	j = FIELD_GET(I40E_PF_VT_PFALLOC_LASTVF_MASK, val);

	if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i)

		num_vfs = (j - i) + 1;

	else
@@ -1194,8 +1187,7 @@ static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 
	    !hw->func_caps.led[idx])

		return 0;

	gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));

	port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>

		I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;

	port = FIELD_GET(I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK, gpio_val);



	/* if PRT_NUM_NA is 1 then this LED is not port specific, OR

	 * if it is not our port then ignore
@@ -1239,8 +1231,7 @@ u32 i40e_led_get(struct i40e_hw *hw) 
		if (!gpio_val)

			continue;



		mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>

			I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;

		mode = FIELD_GET(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, gpio_val);

		break;

	}
@@ -4190,8 +4181,7 @@ i40e_validate_filter_settings(struct i40e_hw *hw, 


	/* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */

	val = rd32(hw, I40E_GLHMC_FCOEFMAX);

	fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)

		     >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;

	fcoe_fmax = FIELD_GET(I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK, val);

	if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)

		return -EINVAL;
@@ -4646,8 +4636,7 @@ int i40e_read_phy_register_clause22(struct i40e_hw *hw, 
			   "PHY: Can't write command to external PHY.\n");

	} else {

		command = rd32(hw, I40E_GLGEN_MSRWD(port_num));

		*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>

			 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;

		*value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command);

	}



	return status;
@@ -4756,8 +4745,7 @@ int i40e_read_phy_register_clause45(struct i40e_hw *hw, 


	if (!status) {

		command = rd32(hw, I40E_GLGEN_MSRWD(port_num));

		*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>

			 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;

		*value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command);

	} else {

		i40e_debug(hw, I40E_DEBUG_PHY,

			   "PHY: Can't read register value from external PHY.\n");
@@ -5902,9 +5890,8 @@ i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 
		u16 tnl_type;

		u32 ti;



		tnl_type = (le16_to_cpu(filters[i].element.flags) &

			   I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>

			   I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;

		tnl_type = le16_get_bits(filters[i].element.flags,

					 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK);



		/* Due to hardware eccentricities, the VNI for Geneve is shifted

		 * one more byte further than normally used for Tenant ID in
@@ -5996,9 +5983,8 @@ i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 
		u16 tnl_type;

		u32 ti;



		tnl_type = (le16_to_cpu(filters[i].element.flags) &

			   I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>

			   I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;

		tnl_type = le16_get_bits(filters[i].element.flags,

					 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK);



		/* Due to hardware eccentricities, the VNI for Geneve is shifted

		 * one more byte further than normally used for Tenant ID in

drivers/net/ethernet/intel/i40e/i40e_dcb.c

+60 −98
Original line number Diff line number Diff line
@@ -22,8 +22,7 @@ int i40e_get_dcbx_status(struct i40e_hw *hw, u16 *status) 
		return -EINVAL;



	reg = rd32(hw, I40E_PRTDCB_GENS);

	*status = (u16)((reg & I40E_PRTDCB_GENS_DCBX_STATUS_MASK) >>

			I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT);

	*status = FIELD_GET(I40E_PRTDCB_GENS_DCBX_STATUS_MASK, reg);



	return 0;

}
@@ -52,12 +51,9 @@ static void i40e_parse_ieee_etscfg_tlv(struct i40e_lldp_org_tlv *tlv, 
	 * |1bit | 1bit|3 bits|3bits|

	 */

	etscfg = &dcbcfg->etscfg;

	etscfg->willing = (u8)((buf[offset] & I40E_IEEE_ETS_WILLING_MASK) >>

			       I40E_IEEE_ETS_WILLING_SHIFT);

	etscfg->cbs = (u8)((buf[offset] & I40E_IEEE_ETS_CBS_MASK) >>

			   I40E_IEEE_ETS_CBS_SHIFT);

	etscfg->maxtcs = (u8)((buf[offset] & I40E_IEEE_ETS_MAXTC_MASK) >>

			      I40E_IEEE_ETS_MAXTC_SHIFT);

	etscfg->willing = FIELD_GET(I40E_IEEE_ETS_WILLING_MASK, buf[offset]);

	etscfg->cbs = FIELD_GET(I40E_IEEE_ETS_CBS_MASK, buf[offset]);

	etscfg->maxtcs = FIELD_GET(I40E_IEEE_ETS_MAXTC_MASK, buf[offset]);



	/* Move offset to Priority Assignment Table */

	offset++;
@@ -71,11 +67,9 @@ static void i40e_parse_ieee_etscfg_tlv(struct i40e_lldp_org_tlv *tlv, 
	 *        -----------------------------------------

	 */

	for (i = 0; i < 4; i++) {

		priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_1_MASK) >>

				I40E_IEEE_ETS_PRIO_1_SHIFT);

		priority = FIELD_GET(I40E_IEEE_ETS_PRIO_1_MASK, buf[offset]);

		etscfg->prioritytable[i * 2] = priority;

		priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_0_MASK) >>

				I40E_IEEE_ETS_PRIO_0_SHIFT);

		priority = FIELD_GET(I40E_IEEE_ETS_PRIO_0_MASK, buf[offset]);

		etscfg->prioritytable[i * 2 + 1] = priority;

		offset++;

	}
@@ -126,12 +120,10 @@ static void i40e_parse_ieee_etsrec_tlv(struct i40e_lldp_org_tlv *tlv, 
	 *        -----------------------------------------

	 */

	for (i = 0; i < 4; i++) {

		priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_1_MASK) >>

				I40E_IEEE_ETS_PRIO_1_SHIFT);

		priority = FIELD_GET(I40E_IEEE_ETS_PRIO_1_MASK, buf[offset]);

		dcbcfg->etsrec.prioritytable[i * 2] = priority;

		priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_0_MASK) >>

				I40E_IEEE_ETS_PRIO_0_SHIFT);

		dcbcfg->etsrec.prioritytable[i*2 + 1] = priority;

		priority = FIELD_GET(I40E_IEEE_ETS_PRIO_0_MASK, buf[offset]);

		dcbcfg->etsrec.prioritytable[(i * 2) + 1] = priority;

		offset++;

	}
@@ -172,12 +164,9 @@ static void i40e_parse_ieee_pfccfg_tlv(struct i40e_lldp_org_tlv *tlv, 
	 * -----------------------------------------

	 * |1bit | 1bit|2 bits|4bits| 1 octet      |

	 */

	dcbcfg->pfc.willing = (u8)((buf[0] & I40E_IEEE_PFC_WILLING_MASK) >>

				   I40E_IEEE_PFC_WILLING_SHIFT);

	dcbcfg->pfc.mbc = (u8)((buf[0] & I40E_IEEE_PFC_MBC_MASK) >>

			       I40E_IEEE_PFC_MBC_SHIFT);

	dcbcfg->pfc.pfccap = (u8)((buf[0] & I40E_IEEE_PFC_CAP_MASK) >>

				  I40E_IEEE_PFC_CAP_SHIFT);

	dcbcfg->pfc.willing = FIELD_GET(I40E_IEEE_PFC_WILLING_MASK, buf[0]);

	dcbcfg->pfc.mbc = FIELD_GET(I40E_IEEE_PFC_MBC_MASK, buf[0]);

	dcbcfg->pfc.pfccap = FIELD_GET(I40E_IEEE_PFC_CAP_MASK, buf[0]);

	dcbcfg->pfc.pfcenable = buf[1];

}
@@ -198,8 +187,7 @@ static void i40e_parse_ieee_app_tlv(struct i40e_lldp_org_tlv *tlv, 
	u8 *buf;



	typelength = ntohs(tlv->typelength);

	length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>

		       I40E_LLDP_TLV_LEN_SHIFT);

	length = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength);

	buf = tlv->tlvinfo;



	/* The App priority table starts 5 octets after TLV header */
@@ -217,12 +205,10 @@ static void i40e_parse_ieee_app_tlv(struct i40e_lldp_org_tlv *tlv, 
	 *        -----------------------------------------

	 */

	while (offset < length) {

		dcbcfg->app[i].priority = (u8)((buf[offset] &

						I40E_IEEE_APP_PRIO_MASK) >>

					       I40E_IEEE_APP_PRIO_SHIFT);

		dcbcfg->app[i].selector = (u8)((buf[offset] &

						I40E_IEEE_APP_SEL_MASK) >>

					       I40E_IEEE_APP_SEL_SHIFT);

		dcbcfg->app[i].priority = FIELD_GET(I40E_IEEE_APP_PRIO_MASK,

						    buf[offset]);

		dcbcfg->app[i].selector = FIELD_GET(I40E_IEEE_APP_SEL_MASK,

						    buf[offset]);

		dcbcfg->app[i].protocolid = (buf[offset + 1] << 0x8) |

					     buf[offset + 2];

		/* Move to next app */
@@ -250,8 +236,7 @@ static void i40e_parse_ieee_tlv(struct i40e_lldp_org_tlv *tlv, 
	u8 subtype;



	ouisubtype = ntohl(tlv->ouisubtype);

	subtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >>

		       I40E_LLDP_TLV_SUBTYPE_SHIFT);

	subtype = FIELD_GET(I40E_LLDP_TLV_SUBTYPE_MASK, ouisubtype);

	switch (subtype) {

	case I40E_IEEE_SUBTYPE_ETS_CFG:

		i40e_parse_ieee_etscfg_tlv(tlv, dcbcfg);
@@ -301,11 +286,9 @@ static void i40e_parse_cee_pgcfg_tlv(struct i40e_cee_feat_tlv *tlv, 
	 *        -----------------------------------------

	 */

	for (i = 0; i < 4; i++) {

		priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_1_MASK) >>

				 I40E_CEE_PGID_PRIO_1_SHIFT);

		priority = FIELD_GET(I40E_CEE_PGID_PRIO_1_MASK, buf[offset]);

		etscfg->prioritytable[i * 2] = priority;

		priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_0_MASK) >>

				 I40E_CEE_PGID_PRIO_0_SHIFT);

		priority = FIELD_GET(I40E_CEE_PGID_PRIO_0_MASK, buf[offset]);

		etscfg->prioritytable[i * 2 + 1] = priority;

		offset++;

	}
@@ -362,8 +345,7 @@ static void i40e_parse_cee_app_tlv(struct i40e_cee_feat_tlv *tlv, 
	u8 i;



	typelength = ntohs(tlv->hdr.typelen);

	length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>

		       I40E_LLDP_TLV_LEN_SHIFT);

	length = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength);



	dcbcfg->numapps = length / sizeof(*app);
@@ -419,15 +401,13 @@ static void i40e_parse_cee_tlv(struct i40e_lldp_org_tlv *tlv, 
	u32 ouisubtype;



	ouisubtype = ntohl(tlv->ouisubtype);

	subtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >>

		       I40E_LLDP_TLV_SUBTYPE_SHIFT);

	subtype = FIELD_GET(I40E_LLDP_TLV_SUBTYPE_MASK, ouisubtype);

	/* Return if not CEE DCBX */

	if (subtype != I40E_CEE_DCBX_TYPE)

		return;



	typelength = ntohs(tlv->typelength);

	tlvlen = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>

			I40E_LLDP_TLV_LEN_SHIFT);

	tlvlen = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength);

	len = sizeof(tlv->typelength) + sizeof(ouisubtype) +

	      sizeof(struct i40e_cee_ctrl_tlv);

	/* Return if no CEE DCBX Feature TLVs */
@@ -437,11 +417,8 @@ static void i40e_parse_cee_tlv(struct i40e_lldp_org_tlv *tlv, 
	sub_tlv = (struct i40e_cee_feat_tlv *)((char *)tlv + len);

	while (feat_tlv_count < I40E_CEE_MAX_FEAT_TYPE) {

		typelength = ntohs(sub_tlv->hdr.typelen);

		sublen = (u16)((typelength &

				I40E_LLDP_TLV_LEN_MASK) >>

				I40E_LLDP_TLV_LEN_SHIFT);

		subtype = (u8)((typelength & I40E_LLDP_TLV_TYPE_MASK) >>

				I40E_LLDP_TLV_TYPE_SHIFT);

		sublen = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength);

		subtype = FIELD_GET(I40E_LLDP_TLV_TYPE_MASK, typelength);

		switch (subtype) {

		case I40E_CEE_SUBTYPE_PG_CFG:

			i40e_parse_cee_pgcfg_tlv(sub_tlv, dcbcfg);
@@ -478,8 +455,7 @@ static void i40e_parse_org_tlv(struct i40e_lldp_org_tlv *tlv, 
	u32 oui;



	ouisubtype = ntohl(tlv->ouisubtype);

	oui = (u32)((ouisubtype & I40E_LLDP_TLV_OUI_MASK) >>

		    I40E_LLDP_TLV_OUI_SHIFT);

	oui = FIELD_GET(I40E_LLDP_TLV_OUI_MASK, ouisubtype);

	switch (oui) {

	case I40E_IEEE_8021QAZ_OUI:

		i40e_parse_ieee_tlv(tlv, dcbcfg);
@@ -517,10 +493,8 @@ int i40e_lldp_to_dcb_config(u8 *lldpmib, 
	tlv = (struct i40e_lldp_org_tlv *)lldpmib;

	while (1) {

		typelength = ntohs(tlv->typelength);

		type = (u16)((typelength & I40E_LLDP_TLV_TYPE_MASK) >>

			     I40E_LLDP_TLV_TYPE_SHIFT);

		length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>

			       I40E_LLDP_TLV_LEN_SHIFT);

		type = FIELD_GET(I40E_LLDP_TLV_TYPE_MASK, typelength);

		length = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength);

		offset += sizeof(typelength) + length;



		/* END TLV or beyond LLDPDU size */
@@ -594,7 +568,7 @@ static void i40e_cee_to_dcb_v1_config( 
{

	u16 status, tlv_status = le16_to_cpu(cee_cfg->tlv_status);

	u16 app_prio = le16_to_cpu(cee_cfg->oper_app_prio);

	u8 i, tc, err;

	u8 i, err;



	/* CEE PG data to ETS config */

	dcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc;
@@ -603,13 +577,13 @@ static void i40e_cee_to_dcb_v1_config( 
	 * from those in the CEE Priority Group sub-TLV.

	 */

	for (i = 0; i < 4; i++) {

		tc = (u8)((cee_cfg->oper_prio_tc[i] &

			 I40E_CEE_PGID_PRIO_0_MASK) >>

			 I40E_CEE_PGID_PRIO_0_SHIFT);

		u8 tc;



		tc = FIELD_GET(I40E_CEE_PGID_PRIO_0_MASK,

			       cee_cfg->oper_prio_tc[i]);

		dcbcfg->etscfg.prioritytable[i * 2] = tc;

		tc = (u8)((cee_cfg->oper_prio_tc[i] &

			 I40E_CEE_PGID_PRIO_1_MASK) >>

			 I40E_CEE_PGID_PRIO_1_SHIFT);

		tc = FIELD_GET(I40E_CEE_PGID_PRIO_1_MASK,

			       cee_cfg->oper_prio_tc[i]);

		dcbcfg->etscfg.prioritytable[i*2 + 1] = tc;

	}
@@ -631,8 +605,7 @@ static void i40e_cee_to_dcb_v1_config( 
	dcbcfg->pfc.pfcenable = cee_cfg->oper_pfc_en;

	dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;



	status = (tlv_status & I40E_AQC_CEE_APP_STATUS_MASK) >>

		  I40E_AQC_CEE_APP_STATUS_SHIFT;

	status = FIELD_GET(I40E_AQC_CEE_APP_STATUS_MASK, tlv_status);

	err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;

	/* Add APPs if Error is False */

	if (!err) {
@@ -641,22 +614,19 @@ static void i40e_cee_to_dcb_v1_config( 


		/* FCoE APP */

		dcbcfg->app[0].priority =

			(app_prio & I40E_AQC_CEE_APP_FCOE_MASK) >>

			 I40E_AQC_CEE_APP_FCOE_SHIFT;

			FIELD_GET(I40E_AQC_CEE_APP_FCOE_MASK, app_prio);

		dcbcfg->app[0].selector = I40E_APP_SEL_ETHTYPE;

		dcbcfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;



		/* iSCSI APP */

		dcbcfg->app[1].priority =

			(app_prio & I40E_AQC_CEE_APP_ISCSI_MASK) >>

			 I40E_AQC_CEE_APP_ISCSI_SHIFT;

			FIELD_GET(I40E_AQC_CEE_APP_ISCSI_MASK, app_prio);

		dcbcfg->app[1].selector = I40E_APP_SEL_TCPIP;

		dcbcfg->app[1].protocolid = I40E_APP_PROTOID_ISCSI;



		/* FIP APP */

		dcbcfg->app[2].priority =

			(app_prio & I40E_AQC_CEE_APP_FIP_MASK) >>

			 I40E_AQC_CEE_APP_FIP_SHIFT;

			FIELD_GET(I40E_AQC_CEE_APP_FIP_MASK, app_prio);

		dcbcfg->app[2].selector = I40E_APP_SEL_ETHTYPE;

		dcbcfg->app[2].protocolid = I40E_APP_PROTOID_FIP;

	}
@@ -675,7 +645,7 @@ static void i40e_cee_to_dcb_config( 
{

	u32 status, tlv_status = le32_to_cpu(cee_cfg->tlv_status);

	u16 app_prio = le16_to_cpu(cee_cfg->oper_app_prio);

	u8 i, tc, err, sync, oper;

	u8 i, err, sync, oper;



	/* CEE PG data to ETS config */

	dcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc;
@@ -684,13 +654,13 @@ static void i40e_cee_to_dcb_config( 
	 * from those in the CEE Priority Group sub-TLV.

	 */

	for (i = 0; i < 4; i++) {

		tc = (u8)((cee_cfg->oper_prio_tc[i] &

			 I40E_CEE_PGID_PRIO_0_MASK) >>

			 I40E_CEE_PGID_PRIO_0_SHIFT);

		u8 tc;



		tc = FIELD_GET(I40E_CEE_PGID_PRIO_0_MASK,

			       cee_cfg->oper_prio_tc[i]);

		dcbcfg->etscfg.prioritytable[i * 2] = tc;

		tc = (u8)((cee_cfg->oper_prio_tc[i] &

			 I40E_CEE_PGID_PRIO_1_MASK) >>

			 I40E_CEE_PGID_PRIO_1_SHIFT);

		tc = FIELD_GET(I40E_CEE_PGID_PRIO_1_MASK,

			       cee_cfg->oper_prio_tc[i]);

		dcbcfg->etscfg.prioritytable[i * 2 + 1] = tc;

	}
@@ -713,8 +683,7 @@ static void i40e_cee_to_dcb_config( 
	dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;



	i = 0;

	status = (tlv_status & I40E_AQC_CEE_FCOE_STATUS_MASK) >>

		  I40E_AQC_CEE_FCOE_STATUS_SHIFT;

	status = FIELD_GET(I40E_AQC_CEE_FCOE_STATUS_MASK, tlv_status);

	err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;

	sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;

	oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;
@@ -722,15 +691,13 @@ static void i40e_cee_to_dcb_config( 
	if (!err && sync && oper) {

		/* FCoE APP */

		dcbcfg->app[i].priority =

			(app_prio & I40E_AQC_CEE_APP_FCOE_MASK) >>

			 I40E_AQC_CEE_APP_FCOE_SHIFT;

			FIELD_GET(I40E_AQC_CEE_APP_FCOE_MASK, app_prio);

		dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE;

		dcbcfg->app[i].protocolid = I40E_APP_PROTOID_FCOE;

		i++;

	}



	status = (tlv_status & I40E_AQC_CEE_ISCSI_STATUS_MASK) >>

		  I40E_AQC_CEE_ISCSI_STATUS_SHIFT;

	status = FIELD_GET(I40E_AQC_CEE_ISCSI_STATUS_MASK, tlv_status);

	err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;

	sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;

	oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;
@@ -738,15 +705,13 @@ static void i40e_cee_to_dcb_config( 
	if (!err && sync && oper) {

		/* iSCSI APP */

		dcbcfg->app[i].priority =

			(app_prio & I40E_AQC_CEE_APP_ISCSI_MASK) >>

			 I40E_AQC_CEE_APP_ISCSI_SHIFT;

			FIELD_GET(I40E_AQC_CEE_APP_ISCSI_MASK, app_prio);

		dcbcfg->app[i].selector = I40E_APP_SEL_TCPIP;

		dcbcfg->app[i].protocolid = I40E_APP_PROTOID_ISCSI;

		i++;

	}



	status = (tlv_status & I40E_AQC_CEE_FIP_STATUS_MASK) >>

		  I40E_AQC_CEE_FIP_STATUS_SHIFT;

	status = FIELD_GET(I40E_AQC_CEE_FIP_STATUS_MASK, tlv_status);

	err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;

	sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;

	oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;
@@ -754,8 +719,7 @@ static void i40e_cee_to_dcb_config( 
	if (!err && sync && oper) {

		/* FIP APP */

		dcbcfg->app[i].priority =

			(app_prio & I40E_AQC_CEE_APP_FIP_MASK) >>

			 I40E_AQC_CEE_APP_FIP_SHIFT;

			FIELD_GET(I40E_AQC_CEE_APP_FIP_MASK, app_prio);

		dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE;

		dcbcfg->app[i].protocolid = I40E_APP_PROTOID_FIP;

		i++;
@@ -1284,8 +1248,7 @@ int i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen, 
	do {

		i40e_add_dcb_tlv(tlv, dcbcfg, tlvid++);

		typelength = ntohs(tlv->typelength);

		length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>

				I40E_LLDP_TLV_LEN_SHIFT);

		length = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength);

		if (length)

			offset += length + I40E_IEEE_TLV_HEADER_LENGTH;

		/* END TLV or beyond LLDPDU size */
@@ -1537,8 +1500,7 @@ u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw) 
{

	u32 reg = rd32(hw, I40E_PRTDCB_GENC);



	return (u8)((reg & I40E_PRTDCB_GENC_NUMTC_MASK) >>

		I40E_PRTDCB_GENC_NUMTC_SHIFT);

	return FIELD_GET(I40E_PRTDCB_GENC_NUMTC_MASK, reg);

}



/**

drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c

+1 −2
Original line number Diff line number Diff line
@@ -21,8 +21,7 @@ static void i40e_get_pfc_delay(struct i40e_hw *hw, u16 *delay) 
	u32 val;



	val = rd32(hw, I40E_PRTDCB_GENC);

	*delay = (u16)((val & I40E_PRTDCB_GENC_PFCLDA_MASK) >>

		       I40E_PRTDCB_GENC_PFCLDA_SHIFT);

	*delay = FIELD_GET(I40E_PRTDCB_GENC_PFCLDA_MASK, val);

}



/**

drivers/net/ethernet/intel/i40e/i40e_ddp.c

+2 −2
Original line number Diff line number Diff line
@@ -81,8 +81,8 @@ static int i40e_ddp_does_profile_exist(struct i40e_hw *hw, 
static bool i40e_ddp_profiles_overlap(struct i40e_profile_info *new,

				      struct i40e_profile_info *old)

{

	unsigned int group_id_old = (u8)((old->track_id & 0x00FF0000) >> 16);

	unsigned int group_id_new = (u8)((new->track_id & 0x00FF0000) >> 16);

	unsigned int group_id_old = FIELD_GET(0x00FF0000, old->track_id);

	unsigned int group_id_new = FIELD_GET(0x00FF0000, new->track_id);



	/* 0x00 group must be only the first */

	if (group_id_new == 0)

drivers/net/ethernet/intel/i40e/i40e_ethtool.c

+3 −4
Original line number Diff line number Diff line
@@ -1952,9 +1952,8 @@ static int i40e_get_eeprom_len(struct net_device *netdev) 
		val = X722_EEPROM_SCOPE_LIMIT + 1;

		return val;

	}

	val = (rd32(hw, I40E_GLPCI_LBARCTRL)

		& I40E_GLPCI_LBARCTRL_FL_SIZE_MASK)

		>> I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT;

	val = FIELD_GET(I40E_GLPCI_LBARCTRL_FL_SIZE_MASK,

			rd32(hw, I40E_GLPCI_LBARCTRL));

	/* register returns value in power of 2, 64Kbyte chunks. */

	val = (64 * 1024) * BIT(val);

	return val;
@@ -3284,7 +3283,7 @@ static int i40e_parse_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp, 
	} else if (valid) {

		data->flex_word = value & I40E_USERDEF_FLEX_WORD;

		data->flex_offset =

			(value & I40E_USERDEF_FLEX_OFFSET) >> 16;

			FIELD_GET(I40E_USERDEF_FLEX_OFFSET, value);

		data->flex_filter = true;

	}