clk: qcom: Add Video Clock controller (VIDEOCC) driver for Milos (633a81be) · Commits · git / linux-nf

drivers/clk/qcom/Kconfig

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		@@ -1429,6 +1429,17 @@ config SM_VIDEOCC_7150
		Say Y if you want to support video devices and functionality such as
		video encode and decode.

		config SM_VIDEOCC_MILOS
		tristate "Milos Video Clock Controller"
		depends on ARM64 \|\| COMPILE_TEST
		select SM_GCC_MILOS
		select QCOM_GDSC
		help
		Support for the video clock controller on Qualcomm Technologies, Inc.
		Milos devices.
		Say Y if you want to support video devices and functionality such as
		video encode/decode.

		config SM_VIDEOCC_8150
		tristate "SM8150 Video Clock Controller"
		depends on ARM64 \|\| COMPILE_TEST

drivers/clk/qcom/Makefile

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		@@ -180,6 +180,7 @@ obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
		obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o
		obj-$(CONFIG_SM_VIDEOCC_8450) += videocc-sm8450.o
		obj-$(CONFIG_SM_VIDEOCC_8550) += videocc-sm8550.o
		obj-$(CONFIG_SM_VIDEOCC_MILOS) += videocc-milos.o
		obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
		obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
		obj-$(CONFIG_QCOM_HFPLL) += hfpll.o

drivers/clk/qcom/videocc-milos.c

0 → 100644

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		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
		* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
		*/

		#include <linux/clk-provider.h>
		#include <linux/mod_devicetable.h>
		#include <linux/module.h>
		#include <linux/platform_device.h>
		#include <linux/regmap.h>

		#include <dt-bindings/clock/qcom,milos-videocc.h>

		#include "clk-alpha-pll.h"
		#include "clk-branch.h"
		#include "clk-rcg.h"
		#include "clk-regmap.h"
		#include "clk-regmap-divider.h"
		#include "common.h"
		#include "gdsc.h"
		#include "reset.h"

		/* Need to match the order of clocks in DT binding */
		enum {
		DT_BI_TCXO,
		DT_BI_TCXO_AO,
		DT_SLEEP_CLK,
		DT_IFACE,
		};

		enum {
		P_BI_TCXO,
		P_SLEEP_CLK,
		P_VIDEO_CC_PLL0_OUT_MAIN,
		};

		static const struct pll_vco lucid_ole_vco[] = {
		{ 249600000, 2300000000, 0 },
		};

		/* 604.8 MHz Configuration */
		static const struct alpha_pll_config video_cc_pll0_config = {
		.l = 0x1f,
		.alpha = 0x8000,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00182261,
		.config_ctl_hi1_val = 0x82aa299c,
		.test_ctl_val = 0x00000000,
		.test_ctl_hi_val = 0x00000003,
		.test_ctl_hi1_val = 0x00009000,
		.test_ctl_hi2_val = 0x00000034,
		.user_ctl_val = 0x00000000,
		.user_ctl_hi_val = 0x00000005,
		};

		static struct clk_alpha_pll video_cc_pll0 = {
		.offset = 0x0,
		.config = &video_cc_pll0_config,
		.vco_table = lucid_ole_vco,
		.num_vco = ARRAY_SIZE(lucid_ole_vco),
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
		.clkr = {
		.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_pll0",
		.parent_data = &(const struct clk_parent_data) {
		.index = DT_BI_TCXO,
		},
		.num_parents = 1,
		.ops = &clk_alpha_pll_lucid_evo_ops,
		},
		},
		};

		static const struct parent_map video_cc_parent_map_0[] = {
		{ P_BI_TCXO, 0 },
		};

		static const struct clk_parent_data video_cc_parent_data_0[] = {
		{ .index = DT_BI_TCXO },
		};

		static const struct clk_parent_data video_cc_parent_data_0_ao[] = {
		{ .index = DT_BI_TCXO_AO },
		};

		static const struct parent_map video_cc_parent_map_1[] = {
		{ P_BI_TCXO, 0 },
		{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
		};

		static const struct clk_parent_data video_cc_parent_data_1[] = {
		{ .index = DT_BI_TCXO },
		{ .hw = &video_cc_pll0.clkr.hw },
		};

		static const struct parent_map video_cc_parent_map_2[] = {
		{ P_SLEEP_CLK, 0 },
		};

		static const struct clk_parent_data video_cc_parent_data_2_ao[] = {
		{ .index = DT_SLEEP_CLK },
		};

		static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_ahb_clk_src = {
		.cmd_rcgr = 0x8030,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_0,
		.freq_tbl = ftbl_video_cc_ahb_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_ahb_clk_src",
		.parent_data = video_cc_parent_data_0_ao,
		.num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_shared_ops,
		},
		};

		static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
		F(604800000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
		F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
		F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
		F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
		F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
		F(1656000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_mvs0_clk_src = {
		.cmd_rcgr = 0x8000,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_1,
		.freq_tbl = ftbl_video_cc_mvs0_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs0_clk_src",
		.parent_data = video_cc_parent_data_1,
		.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_shared_ops,
		},
		};

		static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
		F(32000, P_SLEEP_CLK, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_sleep_clk_src = {
		.cmd_rcgr = 0x8128,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_2,
		.freq_tbl = ftbl_video_cc_sleep_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_sleep_clk_src",
		.parent_data = video_cc_parent_data_2_ao,
		.num_parents = ARRAY_SIZE(video_cc_parent_data_2_ao),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		},
		};

		static struct clk_rcg2 video_cc_xo_clk_src = {
		.cmd_rcgr = 0x810c,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_0,
		.freq_tbl = ftbl_video_cc_ahb_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_xo_clk_src",
		.parent_data = video_cc_parent_data_0,
		.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		},
		};

		static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
		.reg = 0x80c4,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs0_div_clk_src",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_mvs0_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
		.reg = 0x8070,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs0c_div2_div_clk_src",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_mvs0_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_branch video_cc_mvs0_clk = {
		.halt_reg = 0x80b8,
		.halt_check = BRANCH_HALT_VOTED,
		.hwcg_reg = 0x80b8,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0x80b8,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs0_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_mvs0_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs0_shift_clk = {
		.halt_reg = 0x8144,
		.halt_check = BRANCH_HALT_VOTED,
		.hwcg_reg = 0x8144,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0x8144,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs0_shift_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_xo_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs0c_clk = {
		.halt_reg = 0x8064,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x8064,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs0c_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs0c_shift_clk = {
		.halt_reg = 0x8148,
		.halt_check = BRANCH_HALT_VOTED,
		.hwcg_reg = 0x8148,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0x8148,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "video_cc_mvs0c_shift_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&video_cc_xo_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct gdsc video_cc_mvs0c_gdsc = {
		.gdscr = 0x804c,
		.en_rest_wait_val = 0x2,
		.en_few_wait_val = 0x2,
		.clk_dis_wait_val = 0x6,
		.pd = {
		.name = "video_cc_mvs0c_gdsc",
		},
		.pwrsts = PWRSTS_OFF_ON,
		.flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE,
		};

		static struct gdsc video_cc_mvs0_gdsc = {
		.gdscr = 0x80a4,
		.en_rest_wait_val = 0x2,
		.en_few_wait_val = 0x2,
		.clk_dis_wait_val = 0x6,
		.pd = {
		.name = "video_cc_mvs0_gdsc",
		},
		.pwrsts = PWRSTS_OFF_ON,
		.parent = &video_cc_mvs0c_gdsc.pd,
		.flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| HW_CTRL_TRIGGER,
		};

		static struct clk_regmap *video_cc_milos_clocks[] = {
		[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
		[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
		[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
		[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
		[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr,
		[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
		[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
		[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr,
		[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
		[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
		[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
		};

		static struct gdsc *video_cc_milos_gdscs[] = {
		[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
		[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
		};

		static const struct qcom_reset_map video_cc_milos_resets[] = {
		[VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },
		[VIDEO_CC_MVS0_BCR] = { 0x80a0 },
		[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
		[VIDEO_CC_MVS0C_BCR] = { 0x8048 },
		};

		static struct clk_alpha_pll *video_cc_milos_plls[] = {
		&video_cc_pll0,
		};

		static u32 video_cc_milos_critical_cbcrs[] = {
		0x80f4, /* VIDEO_CC_AHB_CLK */
		0x8140, /* VIDEO_CC_SLEEP_CLK */
		0x8124, /* VIDEO_CC_XO_CLK */
		};

		static const struct regmap_config video_cc_milos_regmap_config = {
		.reg_bits = 32,
		.reg_stride = 4,
		.val_bits = 32,
		.max_register = 0x9f50,
		.fast_io = true,
		};

		static struct qcom_cc_driver_data video_cc_milos_driver_data = {
		.alpha_plls = video_cc_milos_plls,
		.num_alpha_plls = ARRAY_SIZE(video_cc_milos_plls),
		.clk_cbcrs = video_cc_milos_critical_cbcrs,
		.num_clk_cbcrs = ARRAY_SIZE(video_cc_milos_critical_cbcrs),
		};

		static struct qcom_cc_desc video_cc_milos_desc = {
		.config = &video_cc_milos_regmap_config,
		.clks = video_cc_milos_clocks,
		.num_clks = ARRAY_SIZE(video_cc_milos_clocks),
		.resets = video_cc_milos_resets,
		.num_resets = ARRAY_SIZE(video_cc_milos_resets),
		.gdscs = video_cc_milos_gdscs,
		.num_gdscs = ARRAY_SIZE(video_cc_milos_gdscs),
		.use_rpm = true,
		.driver_data = &video_cc_milos_driver_data,
		};

		static const struct of_device_id video_cc_milos_match_table[] = {
		{ .compatible = "qcom,milos-videocc" },
		{ }
		};
		MODULE_DEVICE_TABLE(of, video_cc_milos_match_table);

		static int video_cc_milos_probe(struct platform_device *pdev)
		{
		return qcom_cc_probe(pdev, &video_cc_milos_desc);
		}

		static struct platform_driver video_cc_milos_driver = {
		.probe = video_cc_milos_probe,
		.driver = {
		.name = "video_cc-milos",
		.of_match_table = video_cc_milos_match_table,
		},
		};

		module_platform_driver(video_cc_milos_driver);

		MODULE_DESCRIPTION("QTI VIDEO_CC Milos Driver");
		MODULE_LICENSE("GPL");