Commit 63c21d61 authored by Neil Armstrong's avatar Neil Armstrong Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8650: add interconnect and opp-peak-kBps for GPU 



Each GPU OPP requires a specific peak DDR bandwidth, let's add
those to each OPP and also the related interconnect path.

Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241217-topic-sm8x50-gpu-bw-vote-v6-7-1adaf97e7310@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 1ba40079

arch/arm64/boot/dts/qcom/sm8650.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -2636,6 +2636,10 @@ gpu: gpu@3d00000 { 
			qcom,gmu = <&gmu>;

			#cooling-cells = <2>;



			interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS

					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;

			interconnect-names = "gfx-mem";



			status = "disabled";



			zap-shader {
@@ -2649,56 +2653,67 @@ gpu_opp_table: opp-table { 
				opp-231000000 {

					opp-hz = /bits/ 64 <231000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;

					opp-peak-kBps = <2136718>;

				};



				opp-310000000 {

					opp-hz = /bits/ 64 <310000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;

					opp-peak-kBps = <2136718>;

				};



				opp-366000000 {

					opp-hz = /bits/ 64 <366000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;

					opp-peak-kBps = <6074218>;

				};



				opp-422000000 {

					opp-hz = /bits/ 64 <422000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

					opp-peak-kBps = <8171875>;

				};



				opp-500000000 {

					opp-hz = /bits/ 64 <500000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;

					opp-peak-kBps = <8171875>;

				};



				opp-578000000 {

					opp-hz = /bits/ 64 <578000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

					opp-peak-kBps = <8171875>;

				};



				opp-629000000 {

					opp-hz = /bits/ 64 <629000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;

					opp-peak-kBps = <10687500>;

				};



				opp-680000000 {

					opp-hz = /bits/ 64 <680000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

					opp-peak-kBps = <12449218>;

				};



				opp-720000000 {

					opp-hz = /bits/ 64 <720000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;

					opp-peak-kBps = <12449218>;

				};



				opp-770000000 {

					opp-hz = /bits/ 64 <770000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;

					opp-peak-kBps = <12449218>;

				};



				opp-834000000 {

					opp-hz = /bits/ 64 <834000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

					opp-peak-kBps = <14398437>;

				};

			};

		};