Commit 63c81af1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_6.13_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS updates from Thomas Bogendoerfer:

 - fix for loongson64 device tree

 - add SPI nand to realtek device tree

 - change clock tree for mobileye

* tag 'mips_6.13_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: Loongson64: DTS: Really fix PCIe port nodes for ls7a
  mips: dts: realtek: Add SPI NAND controller
  MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks
  MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks
parents 9d5daef3 4fbd66d8

arch/mips/boot/dts/loongson/ls7a-pch.dtsi

+60 −13
Original line number Diff line number Diff line
@@ -70,7 +70,6 @@ pci@1a000000 { 
			device_type = "pci";

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <2>;

			msi-parent = <&msi>;



			reg = <0 0x1a000000 0 0x02000000>,
@@ -234,7 +233,7 @@ phy1: ethernet-phy@1 { 
				};

			};



			pci_bridge@9,0 {

			pcie@9,0 {

				compatible = "pci0014,7a19.1",

						   "pci0014,7a19",

						   "pciclass060400",
@@ -244,12 +243,16 @@ pci_bridge@9,0 { 
				interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&pic>;



				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;

				ranges;

			};



			pci_bridge@a,0 {

			pcie@a,0 {

				compatible = "pci0014,7a09.1",

						   "pci0014,7a09",

						   "pciclass060400",
@@ -259,12 +262,16 @@ pci_bridge@a,0 { 
				interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&pic>;



				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;

				ranges;

			};



			pci_bridge@b,0 {

			pcie@b,0 {

				compatible = "pci0014,7a09.1",

						   "pci0014,7a09",

						   "pciclass060400",
@@ -274,12 +281,16 @@ pci_bridge@b,0 { 
				interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&pic>;



				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;

				ranges;

			};



			pci_bridge@c,0 {

			pcie@c,0 {

				compatible = "pci0014,7a09.1",

						   "pci0014,7a09",

						   "pciclass060400",
@@ -289,12 +300,16 @@ pci_bridge@c,0 { 
				interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&pic>;



				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;

				ranges;

			};



			pci_bridge@d,0 {

			pcie@d,0 {

				compatible = "pci0014,7a19.1",

						   "pci0014,7a19",

						   "pciclass060400",
@@ -304,12 +319,16 @@ pci_bridge@d,0 { 
				interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&pic>;



				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;

				ranges;

			};



			pci_bridge@e,0 {

			pcie@e,0 {

				compatible = "pci0014,7a09.1",

						   "pci0014,7a09",

						   "pciclass060400",
@@ -319,12 +338,16 @@ pci_bridge@e,0 { 
				interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&pic>;



				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;

				ranges;

			};



			pci_bridge@f,0 {

			pcie@f,0 {

				compatible = "pci0014,7a29.1",

						   "pci0014,7a29",

						   "pciclass060400",
@@ -334,12 +357,16 @@ pci_bridge@f,0 { 
				interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&pic>;



				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;

				ranges;

			};



			pci_bridge@10,0 {

			pcie@10,0 {

				compatible = "pci0014,7a19.1",

						   "pci0014,7a19",

						   "pciclass060400",
@@ -349,12 +376,16 @@ pci_bridge@10,0 { 
				interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&pic>;



				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;

				ranges;

			};



			pci_bridge@11,0 {

			pcie@11,0 {

				compatible = "pci0014,7a29.1",

						   "pci0014,7a29",

						   "pciclass060400",
@@ -364,12 +395,16 @@ pci_bridge@11,0 { 
				interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&pic>;



				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;

				ranges;

			};



			pci_bridge@12,0 {

			pcie@12,0 {

				compatible = "pci0014,7a19.1",

						   "pci0014,7a19",

						   "pciclass060400",
@@ -379,12 +414,16 @@ pci_bridge@12,0 { 
				interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&pic>;



				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;

				ranges;

			};



			pci_bridge@13,0 {

			pcie@13,0 {

				compatible = "pci0014,7a29.1",

						   "pci0014,7a29",

						   "pciclass060400",
@@ -394,12 +433,16 @@ pci_bridge@13,0 { 
				interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&pic>;



				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;

				ranges;

			};



			pci_bridge@14,0 {

			pcie@14,0 {

				compatible = "pci0014,7a19.1",

						   "pci0014,7a19",

						   "pciclass060400",
@@ -409,9 +452,13 @@ pci_bridge@14,0 { 
				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&pic>;



				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;

				ranges;

			};

		};

arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi

deleted100644 → 0
+0 −270
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

/*

 * Copyright 2023 Mobileye Vision Technologies Ltd.

 */



#include <dt-bindings/clock/mobileye,eyeq5-clk.h>



/ {

	/* Fixed clock */

	xtal: xtal {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <30000000>;

	};



/* PLL_CPU derivatives */

	occ_cpu: occ-cpu {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_CPU>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */

		compatible = "fixed-factor-clock";

		clocks = <&occ_cpu>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	cpc_clk: cpc-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	core0_clk: core0-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	core1_clk: core1-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	core2_clk: core2-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	core3_clk: core3-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	cm_clk: cm-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	mem_clk: mem-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	occ_isram: occ-isram {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_CPU>;

		#clock-cells = <0>;

		clock-div = <2>;

		clock-mult = <1>;

	};

	isram_clk: isram-clk { /* gate ClkRstGen_isram */

		compatible = "fixed-factor-clock";

		clocks = <&occ_isram>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	occ_dbu: occ-dbu {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_CPU>;

		#clock-cells = <0>;

		clock-div = <10>;

		clock-mult = <1>;

	};

	si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */

		compatible = "fixed-factor-clock";

		clocks = <&occ_dbu>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

/* PLL_VDI derivatives */

	occ_vdi: occ-vdi {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_VDI>;

		#clock-cells = <0>;

		clock-div = <2>;

		clock-mult = <1>;

	};

	vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */

		compatible = "fixed-factor-clock";

		clocks = <&occ_vdi>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	occ_can_ser: occ-can-ser {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_VDI>;

		#clock-cells = <0>;

		clock-div = <16>;

		clock-mult = <1>;

	};

	can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */

		compatible = "fixed-factor-clock";

		clocks = <&occ_can_ser>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	i2c_ser_clk: i2c-ser-clk {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_VDI>;

		#clock-cells = <0>;

		clock-div = <20>;

		clock-mult = <1>;

	};

/* PLL_PER derivatives */

	occ_periph: occ-periph {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_PER>;

		#clock-cells = <0>;

		clock-div = <16>;

		clock-mult = <1>;

	};

	periph_clk: periph-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	can_clk: can-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	spi_clk: spi-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	uart_clk: uart-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	i2c_clk: i2c-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

		clock-output-names = "i2c_clk";

	};

	timer_clk: timer-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

		clock-output-names = "timer_clk";

	};

	gpio_clk: gpio-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

		clock-output-names = "gpio_clk";

	};

	emmc_sys_clk: emmc-sys-clk {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_PER>;

		#clock-cells = <0>;

		clock-div = <10>;

		clock-mult = <1>;

		clock-output-names = "emmc_sys_clk";

	};

	ccf_ctrl_clk: ccf-ctrl-clk {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_PER>;

		#clock-cells = <0>;

		clock-div = <4>;

		clock-mult = <1>;

		clock-output-names = "ccf_ctrl_clk";

	};

	occ_mjpeg_core: occ-mjpeg-core {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_PER>;

		#clock-cells = <0>;

		clock-div = <2>;

		clock-mult = <1>;

		clock-output-names = "occ_mjpeg_core";

	};

	hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */

		compatible = "fixed-factor-clock";

		clocks = <&occ_mjpeg_core>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

		clock-output-names = "hsm_clk";

	};

	mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */

		compatible = "fixed-factor-clock";

		clocks = <&occ_mjpeg_core>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

		clock-output-names = "mjpeg_core_clk";

	};

	fcmu_a_clk: fcmu-a-clk {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_PER>;

		#clock-cells = <0>;

		clock-div = <20>;

		clock-mult = <1>;

		clock-output-names = "fcmu_a_clk";

	};

	occ_pci_sys: occ-pci-sys {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_PER>;

		#clock-cells = <0>;

		clock-div = <8>;

		clock-mult = <1>;

		clock-output-names = "occ_pci_sys";

	};

	pclk: pclk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <250000000>;  /* 250MHz */

	};

	tsu_clk: tsu-clk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <125000000>;  /* 125MHz */

	};

};

arch/mips/boot/dts/mobileye/eyeq5.dtsi

+24 −6
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 


#include <dt-bindings/interrupt-controller/mips-gic.h>



#include "eyeq5-clocks.dtsi"

#include <dt-bindings/clock/mobileye,eyeq5-clk.h>



/ {

	#address-cells = <2>;
@@ -17,7 +17,7 @@ cpu@0 { 
			device_type = "cpu";

			compatible = "img,i6500";

			reg = <0>;

			clocks = <&core0_clk>;

			clocks = <&olb EQ5C_CPU_CORE0>;

		};

	};
@@ -64,6 +64,24 @@ cpu_intc: interrupt-controller { 
		#interrupt-cells = <1>;

	};



	xtal: xtal {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <30000000>;

	};



	pclk: pclk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <250000000>;  /* 250MHz */

	};



	tsu_clk: tsu-clk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <125000000>;  /* 125MHz */

	};



	soc: soc {

		#address-cells = <2>;

		#size-cells = <2>;
@@ -76,7 +94,7 @@ uart0: serial@800000 { 
			reg-io-width = <4>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;

			clocks  = <&uart_clk>, <&occ_periph>;

			clocks  = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;

			clock-names = "uartclk", "apb_pclk";

			resets = <&olb 0 10>;

			pinctrl-names = "default";
@@ -89,7 +107,7 @@ uart1: serial@900000 { 
			reg-io-width = <4>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;

			clocks  = <&uart_clk>, <&occ_periph>;

			clocks  = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;

			clock-names = "uartclk", "apb_pclk";

			resets = <&olb 0 11>;

			pinctrl-names = "default";
@@ -102,7 +120,7 @@ uart2: serial@a00000 { 
			reg-io-width = <4>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;

			clocks  = <&uart_clk>, <&occ_periph>;

			clocks  = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;

			clock-names = "uartclk", "apb_pclk";

			resets = <&olb 0 12>;

			pinctrl-names = "default";
@@ -135,7 +153,7 @@ gic: interrupt-controller@140000 { 
			timer {

				compatible = "mti,gic-timer";

				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;

				clocks = <&core0_clk>;

				clocks = <&olb EQ5C_CPU_CORE0>;

			};

		};

	};

arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi

deleted100644 → 0
+0 −52
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

/*

 * Copyright 2023 Mobileye Vision Technologies Ltd.

 */



#include <dt-bindings/clock/mobileye,eyeq5-clk.h>



/ {

	xtal: clock-30000000 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <30000000>;

	};



	pll_west: clock-2000000000-west {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <2000000000>;

	};



	pll_cpu: clock-2000000000-cpu {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <2000000000>;

	};



	/* pll-cpu derivatives */

	occ_cpu: clock-2000000000-occ-cpu {

		compatible = "fixed-factor-clock";

		clocks = <&pll_cpu>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};



	/* pll-west derivatives */

	occ_periph_w: clock-200000000 {

		compatible = "fixed-factor-clock";

		clocks = <&pll_west>;

		#clock-cells = <0>;

		clock-div = <10>;

		clock-mult = <1>;

	};

	uart_clk: clock-200000000-uart {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph_w>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};



};

arch/mips/boot/dts/mobileye/eyeq6h.dtsi

+69 −4
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 


#include <dt-bindings/interrupt-controller/mips-gic.h>



#include "eyeq6h-fixed-clocks.dtsi"

#include <dt-bindings/clock/mobileye,eyeq5-clk.h>



/ {

	#address-cells = <2>;
@@ -17,7 +17,7 @@ cpu@0 { 
			device_type = "cpu";

			compatible = "img,i6500";

			reg = <0>;

			clocks = <&occ_cpu>;

			clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;

		};

	};
@@ -32,19 +32,42 @@ cpu_intc: interrupt-controller { 
		#interrupt-cells = <1>;

	};



	xtal: clock-30000000 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <30000000>;

	};



	soc: soc {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		olb_acc: system-controller@d2003000 {

			compatible = "mobileye,eyeq6h-acc-olb", "syscon";

			reg = <0x0 0xd2003000 0x0 0x1000>;

			#reset-cells = <1>;

			#clock-cells = <1>;

			clocks = <&xtal>;

			clock-names = "ref";

		};



		olb_central: system-controller@d3100000 {

			compatible = "mobileye,eyeq6h-central-olb", "syscon";

			reg = <0x0 0xd3100000 0x0 0x1000>;

			#clock-cells = <1>;

			clocks = <&xtal>;

			clock-names = "ref";

		};



		uart0: serial@d3331000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0 0xd3331000 0x0 0x1000>;

			reg-io-width = <4>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 43 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&occ_periph_w>, <&occ_periph_w>;

			clocks = <&olb_west EQ6HC_WEST_PER_UART>, <&olb_west EQ6HC_WEST_PER_OCC>;

			clock-names = "uartclk", "apb_pclk";

		};
@@ -56,6 +79,15 @@ pinctrl_west: pinctrl@d3337000 { 
			pinctrl-single,function-mask = <0xffff>;

		};



		olb_west: system-controller@d3338000 {

			compatible = "mobileye,eyeq6h-west-olb", "syscon";

			reg = <0x0 0xd3338000 0x0 0x1000>;

			#reset-cells = <1>;

			#clock-cells = <1>;

			clocks = <&xtal>;

			clock-names = "ref";

		};



		pinctrl_east: pinctrl@d3357000 {

			compatible = "pinctrl-single";

			reg = <0x0 0xd3357000 0x0 0xb0>;
@@ -64,6 +96,23 @@ pinctrl_east: pinctrl@d3357000 { 
			pinctrl-single,function-mask = <0xffff>;

		};



		olb_east: system-controller@d3358000 {

			compatible = "mobileye,eyeq6h-east-olb", "syscon";

			reg = <0x0 0xd3358000 0x0 0x1000>;

			#reset-cells = <1>;

			#clock-cells = <1>;

			clocks = <&xtal>;

			clock-names = "ref";

		};



		olb_south: system-controller@d8013000 {

			compatible = "mobileye,eyeq6h-south-olb", "syscon";

			reg = <0x0 0xd8013000 0x0 0x1000>;

			#clock-cells = <1>;

			clocks = <&xtal>;

			clock-names = "ref";

		};



		pinctrl_south: pinctrl@d8014000 {

			compatible = "pinctrl-single";

			reg = <0x0 0xd8014000 0x0 0xf8>;
@@ -72,6 +121,22 @@ pinctrl_south: pinctrl@d8014000 { 
			pinctrl-single,function-mask = <0xffff>;

		};



		olb_ddr0: system-controller@e4080000 {

			compatible = "mobileye,eyeq6h-ddr0-olb", "syscon";

			reg = <0x0 0xe4080000 0x0 0x1000>;

			#clock-cells = <1>;

			clocks = <&xtal>;

			clock-names = "ref";

		};



		olb_ddr1: system-controller@e4081000 {

			compatible = "mobileye,eyeq6h-ddr1-olb", "syscon";

			reg = <0x0 0xe4081000 0x0 0x1000>;

			#clock-cells = <1>;

			clocks = <&xtal>;

			clock-names = "ref";

		};



		gic: interrupt-controller@f0920000 {

			compatible = "mti,gic";

			reg = <0x0 0xf0920000 0x0 0x20000>;
@@ -89,7 +154,7 @@ gic: interrupt-controller@f0920000 { 
			timer {

				compatible = "mti,gic-timer";

				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;

				clocks = <&occ_cpu>;

				clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;

			};

		};

	};