Commit 6a364990 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: change labels to lower-case 



DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-17-0505bc7d2c56@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 4c047c47

arch/arm64/boot/dts/qcom/qcm2290.dtsi

+34 −34
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ cpus { 
		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@0 {

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x0>;
@@ -50,18 +50,18 @@ CPU0: cpu@0 { 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			next-level-cache = <&l2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			power-domains = <&CPU_PD0>;

			power-domains = <&cpu_pd0>;

			power-domain-names = "psci";

			L2_0: l2-cache {

			l2_0: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

			};

		};



		CPU1: cpu@1 {

		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x1>;
@@ -69,13 +69,13 @@ CPU1: cpu@1 { 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			next-level-cache = <&l2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			power-domains = <&CPU_PD1>;

			power-domains = <&cpu_pd1>;

			power-domain-names = "psci";

		};



		CPU2: cpu@2 {

		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x2>;
@@ -83,13 +83,13 @@ CPU2: cpu@2 { 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			next-level-cache = <&l2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			power-domains = <&CPU_PD2>;

			power-domains = <&cpu_pd2>;

			power-domain-names = "psci";

		};



		CPU3: cpu@3 {

		cpu3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x3>;
@@ -97,34 +97,34 @@ CPU3: cpu@3 { 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			next-level-cache = <&l2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			power-domains = <&CPU_PD3>;

			power-domains = <&cpu_pd3>;

			power-domain-names = "psci";

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

					cpu = <&cpu0>;

				};



				core1 {

					cpu = <&CPU1>;

					cpu = <&cpu1>;

				};



				core2 {

					cpu = <&CPU2>;

					cpu = <&cpu2>;

				};



				core3 {

					cpu = <&CPU3>;

					cpu = <&cpu3>;

				};

			};

		};



		domain-idle-states {

			CLUSTER_SLEEP: cluster-sleep-0 {

			cluster_sleep: cluster-sleep-0 {

				compatible = "domain-idle-state";

				arm,psci-suspend-param = <0x41000043>;

				entry-latency-us = <800>;
@@ -136,7 +136,7 @@ CLUSTER_SLEEP: cluster-sleep-0 { 
		idle-states {

			entry-method = "psci";



			CPU_SLEEP: cpu-sleep-0 {

			cpu_sleep: cpu-sleep-0 {

				compatible = "arm,idle-state";

				idle-state-name = "power-collapse";

				arm,psci-suspend-param = <0x40000003>;
@@ -174,34 +174,34 @@ psci { 
		compatible = "arm,psci-1.0";

		method = "smc";



		CPU_PD0: power-domain-cpu0 {

		cpu_pd0: power-domain-cpu0 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&CPU_SLEEP>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&cpu_sleep>;

		};



		CPU_PD1: power-domain-cpu1 {

		cpu_pd1: power-domain-cpu1 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&CPU_SLEEP>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&cpu_sleep>;

		};



		CPU_PD2: power-domain-cpu2 {

		cpu_pd2: power-domain-cpu2 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&CPU_SLEEP>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&cpu_sleep>;

		};



		CPU_PD3: power-domain-cpu3 {

		cpu_pd3: power-domain-cpu3 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&CPU_SLEEP>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&cpu_sleep>;

		};



		CLUSTER_PD: power-domain-cpu-cluster {

		cluster_pd: power-domain-cpu-cluster {

			#power-domain-cells = <0>;

			power-domains = <&mpm>;

			domain-idle-states = <&CLUSTER_SLEEP>;

			domain-idle-states = <&cluster_sleep>;

		};

	};
@@ -2067,7 +2067,7 @@ lmh_cluster: lmh@f550800 { 
			compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh";

			reg = <0x0 0x0f550800 0x0 0x400>;

			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

			cpus = <&CPU0>;

			cpus = <&cpu0>;

			qcom,lmh-temp-arm-millicelsius = <65000>;

			qcom,lmh-temp-low-millicelsius = <94500>;

			qcom,lmh-temp-high-millicelsius = <95000>;

arch/arm64/boot/dts/qcom/qcs404.dtsi

+34 −34
Original line number Diff line number Diff line
@@ -36,13 +36,13 @@ cpus { 
		#address-cells = <1>;

		#size-cells = <0>;



		CPU0: cpu@100 {

		cpu0: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x100>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			next-level-cache = <&L2_0>;

			cpu-idle-states = <&cpu_sleep_0>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

			clocks = <&apcs_glb>;

			operating-points-v2 = <&cpu_opp_table>;
@@ -50,13 +50,13 @@ CPU0: cpu@100 { 
			power-domain-names = "cpr";

		};



		CPU1: cpu@101 {

		cpu1: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x101>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			next-level-cache = <&L2_0>;

			cpu-idle-states = <&cpu_sleep_0>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

			clocks = <&apcs_glb>;

			operating-points-v2 = <&cpu_opp_table>;
@@ -64,13 +64,13 @@ CPU1: cpu@101 { 
			power-domain-names = "cpr";

		};



		CPU2: cpu@102 {

		cpu2: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x102>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			next-level-cache = <&L2_0>;

			cpu-idle-states = <&cpu_sleep_0>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

			clocks = <&apcs_glb>;

			operating-points-v2 = <&cpu_opp_table>;
@@ -78,13 +78,13 @@ CPU2: cpu@102 { 
			power-domain-names = "cpr";

		};



		CPU3: cpu@103 {

		cpu3: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x103>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			next-level-cache = <&L2_0>;

			cpu-idle-states = <&cpu_sleep_0>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

			clocks = <&apcs_glb>;

			operating-points-v2 = <&cpu_opp_table>;
@@ -92,7 +92,7 @@ CPU3: cpu@103 { 
			power-domain-names = "cpr";

		};



		L2_0: l2-cache {

		l2_0: l2-cache {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;
@@ -101,7 +101,7 @@ L2_0: l2-cache { 
		idle-states {

			entry-method = "psci";



			CPU_SLEEP_0: cpu-sleep-0 {

			cpu_sleep_0: cpu-sleep-0 {

				compatible = "arm,idle-state";

				idle-state-name = "standalone-power-collapse";

				arm,psci-suspend-param = <0x40000003>;
@@ -1679,10 +1679,10 @@ cluster_crit: cluster-crit { 
			cooling-maps {

				map0 {

					trip = <&cluster_alert1>;

					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

				};

			};

		};
@@ -1712,10 +1712,10 @@ cpu0_crit: cpu-crit { 
			cooling-maps {

				map0 {

					trip = <&cpu0_alert1>;

					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

				};

			};

		};
@@ -1745,10 +1745,10 @@ cpu1_crit: cpu-crit { 
			cooling-maps {

				map0 {

					trip = <&cpu1_alert1>;

					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

				};

			};

		};
@@ -1778,10 +1778,10 @@ cpu2_crit: cpu-crit { 
			cooling-maps {

				map0 {

					trip = <&cpu2_alert1>;

					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

				};

			};

		};
@@ -1811,10 +1811,10 @@ cpu3_crit: cpu-crit { 
			cooling-maps {

				map0 {

					trip = <&cpu3_alert1>;

					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

						       <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

				};

			};

		};

arch/arm64/boot/dts/qcom/qdu1000.dtsi

+43 −43
Original line number Diff line number Diff line
@@ -25,22 +25,22 @@ cpus { 
		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@0 {

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a55";

			reg = <0x0 0x0>;

			clocks = <&cpufreq_hw 0>;

			enable-method = "psci";

			power-domains = <&CPU_PD0>;

			power-domains = <&cpu_pd0>;

			power-domain-names = "psci";

			qcom,freq-domains = <&cpufreq_hw 0>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			next-level-cache = <&l2_0>;

			l2_0: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				L3_0: l3-cache {

				next-level-cache = <&l3_0>;

				l3_0: l3-cache {

					compatible = "cache";

					cache-level = <3>;

					cache-unified;
@@ -48,76 +48,76 @@ L3_0: l3-cache { 
			};

		};



		CPU1: cpu@100 {

		cpu1: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a55";

			reg = <0x0 0x100>;

			clocks = <&cpufreq_hw 0>;

			enable-method = "psci";

			power-domains = <&CPU_PD1>;

			power-domains = <&cpu_pd1>;

			power-domain-names = "psci";

			qcom,freq-domains = <&cpufreq_hw 0>;

			next-level-cache = <&L2_100>;

			L2_100: l2-cache {

			next-level-cache = <&l2_100>;

			l2_100: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU2: cpu@200 {

		cpu2: cpu@200 {

			device_type = "cpu";

			compatible = "arm,cortex-a55";

			reg = <0x0 0x200>;

			clocks = <&cpufreq_hw 0>;

			enable-method = "psci";

			power-domains = <&CPU_PD2>;

			power-domains = <&cpu_pd2>;

			power-domain-names = "psci";

			qcom,freq-domains = <&cpufreq_hw 0>;

			next-level-cache = <&L2_200>;

			L2_200: l2-cache {

			next-level-cache = <&l2_200>;

			l2_200: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU3: cpu@300 {

		cpu3: cpu@300 {

			device_type = "cpu";

			compatible = "arm,cortex-a55";

			reg = <0x0 0x300>;

			clocks = <&cpufreq_hw 0>;

			enable-method = "psci";

			power-domains = <&CPU_PD3>;

			power-domains = <&cpu_pd3>;

			power-domain-names = "psci";

			qcom,freq-domains = <&cpufreq_hw 0>;

			next-level-cache = <&L2_300>;

			L2_300: l2-cache {

			next-level-cache = <&l2_300>;

			l2_300: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

					cpu = <&cpu0>;

				};



				core1 {

					cpu = <&CPU1>;

					cpu = <&cpu1>;

				};



				core2 {

					cpu = <&CPU2>;

					cpu = <&cpu2>;

				};



				core3 {

					cpu = <&CPU3>;

					cpu = <&cpu3>;

				};

			};

		};
@@ -126,7 +126,7 @@ core3 { 
	idle-states {

		entry-method = "psci";



		CPU_OFF: cpu-sleep-0 {

		cpu_off: cpu-sleep-0 {

			compatible = "arm,idle-state";

			entry-latency-us = <274>;

			exit-latency-us = <480>;
@@ -137,7 +137,7 @@ CPU_OFF: cpu-sleep-0 { 
	};



	domain-idle-states {

		CLUSTER_SLEEP_0: cluster-sleep-0 {

		cluster_sleep_0: cluster-sleep-0 {

			compatible = "domain-idle-state";

			entry-latency-us = <584>;

			exit-latency-us = <2332>;
@@ -145,7 +145,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { 
			arm,psci-suspend-param = <0x41000044>;

		};



		CLUSTER_SLEEP_1: cluster-sleep-1 {

		cluster_sleep_1: cluster-sleep-1 {

			compatible = "domain-idle-state";

			entry-latency-us = <2893>;

			exit-latency-us = <4023>;
@@ -187,33 +187,33 @@ psci { 
		compatible = "arm,psci-1.0";

		method = "smc";



		CPU_PD0: power-domain-cpu0 {

		cpu_pd0: power-domain-cpu0 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&CPU_OFF>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&cpu_off>;

		};



		CPU_PD1: power-domain-cpu1 {

		cpu_pd1: power-domain-cpu1 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&CPU_OFF>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&cpu_off>;

		};



		CPU_PD2: power-domain-cpu2 {

		cpu_pd2: power-domain-cpu2 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&CPU_OFF>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&cpu_off>;

		};



		CPU_PD3: power-domain-cpu3 {

		cpu_pd3: power-domain-cpu3 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&CPU_OFF>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&cpu_off>;

		};



		CLUSTER_PD: power-domain-cluster {

		cluster_pd: power-domain-cluster {

			#power-domain-cells = <0>;

			domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>;

			domain-idle-states = <&cluster_sleep_0 &cluster_sleep_1>;

		};

	};
@@ -1499,7 +1499,7 @@ apps_rsc: rsc@17a00000 { 
			qcom,tcs-config = <ACTIVE_TCS    2>, <SLEEP_TCS     3>,

					  <WAKE_TCS      3>, <CONTROL_TCS   0>;

			label = "apps_rsc";

			power-domains = <&CLUSTER_PD>;

			power-domains = <&cluster_pd>;



			apps_bcm_voter: bcm-voter {

				compatible = "qcom,bcm-voter";

arch/arm64/boot/dts/qcom/qrb2210-rb1.dts

+7 −7
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ chosen { 
	};



	clocks {

		clk40M: can-clk {

		clk40m: can-clk {

			compatible = "fixed-clock";

			clock-frequency = <40000000>;

			#clock-cells = <0>;
@@ -188,23 +188,23 @@ vph_pwr: regulator-vph-pwr { 
	};

};



&CPU_PD0 {

&cpu_pd0 {

	/delete-property/ power-domains;

};



&CPU_PD1 {

&cpu_pd1 {

	/delete-property/ power-domains;

};



&CPU_PD2 {

&cpu_pd2 {

	/delete-property/ power-domains;

};



&CPU_PD3 {

&cpu_pd3 {

	/delete-property/ power-domains;

};



/delete-node/ &CLUSTER_PD;

/delete-node/ &cluster_pd;



&gpi_dma0 {

	status = "okay";
@@ -541,7 +541,7 @@ can@0 { 
		compatible = "microchip,mcp2518fd";

		reg = <0>;

		interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&clk40M>;

		clocks = <&clk40m>;

		spi-max-frequency = <10000000>;

		vdd-supply = <&vdc_5v>;

		xceiver-supply = <&vdc_5v>;

arch/arm64/boot/dts/qcom/sa8775p.dtsi

+94 −94

File changed.

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