Commit 6b340ccc authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: update flip bit setting of RAS bad page 



The flip bit setting is different if umc number is half of original
configuration.

v2: block the flip bit setting for unsupported umc configuration.

Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 736ef29e

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

+80 −33
Original line number Diff line number Diff line
@@ -183,6 +183,7 @@ static void umc_v12_0_get_retire_flip_bits(struct amdgpu_device *adev) 
	if (adev->gmc.gmc_funcs->query_mem_partition_mode)

		nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);



	if (adev->gmc.num_umc == 16) {

		/* default setting */

		flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT;

		flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT;
@@ -228,6 +229,52 @@ static void umc_v12_0_get_retire_flip_bits(struct amdgpu_device *adev) 
				"Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n");

			break;

		}

	} else if (adev->gmc.num_umc == 8) {

		/* default setting */

		flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;

		flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;

		flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;

		flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;

		flip_bits->flip_row_bit = 12;

		flip_bits->bit_num = 4;

		flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;



		if (nps == AMDGPU_NPS2_PARTITION_MODE) {

			flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;

			flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;

			flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;

			flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;

		}



		switch (vram_type) {

		case AMDGPU_VRAM_TYPE_HBM:

			flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;



			/* other nps modes are taken as nps1 */

			if (nps == AMDGPU_NPS2_PARTITION_MODE)

				flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;



			break;

		case AMDGPU_VRAM_TYPE_HBM3E:

			flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;

			flip_bits->flip_row_bit = 12;



			if (nps == AMDGPU_NPS2_PARTITION_MODE)

				flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT;



			break;

		default:

			dev_warn(adev->dev,

				"Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n");

			break;

		}

	} else {

		dev_warn(adev->dev,

			"Unsupported UMC number(%d), failed to set RAS flip bits.\n",

			adev->gmc.num_umc);



		return;

	}



	adev->umc.retire_unit = 0x1 << flip_bits->bit_num;

}