Unverified Commit 6df5678b authored by Gustavo Sousa's avatar Gustavo Sousa Committed by Rodrigo Vivi
Browse files

drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN4 



The register COMMON_SLICE_CHICKEN4 is a MCR register on both Xe2 and
Xe3. Let's make sure to define a MCR version of it and use it for the
relevant IP versions.

Use XEHP_ as prefix for the register name, since it is MCR as of Xe_HP.

v2:
  - Also change for one entry in lrc_tunnings, which was caught by
    manual testing and add corresponging Fixes tag in commit message.
    (Gustavo)

Fixes: 8d6f16f1 ("drm/xe: Extend Wa_22021007897 to Xe3 platforms")
Fixes: e5c13e2c ("drm/xe/xe2hpg: Add Wa_22021007897")
Fixes: 8ccf5f6b ("drm/xe/tuning: Apply windower hardware filtering setting on Xe3 and Xe3p")
Bspec: 66534, 71185, 74417
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260514-rtp-mcr-check-v3-3-30dd47855fee@intel.com


Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
(cherry picked from commit 75f65f1a4c06da1d87f28570a9d4cdad28f13360)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent a4660bd9

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -179,6 +179,7 @@ 
#define XEHPG_SC_INSTDONE_EXTRA2		XE_REG_MCR(0x7108)



#define COMMON_SLICE_CHICKEN4			XE_REG(0x7300, XE_REG_OPTION_MASKED)

#define XEHP_COMMON_SLICE_CHICKEN4		XE_REG_MCR(0x7300, XE_REG_OPTION_MASKED)

#define   SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE	REG_BIT(12)

#define   DISABLE_TDC_LOAD_BALANCING_CALC	REG_BIT(6)

#define   HW_FILTERING				REG_BIT(5)

drivers/gpu/drm/xe/xe_tuning.c

+1 −1
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ static const struct xe_rtp_entry_sr engine_tunings[] = { 
static const struct xe_rtp_entry_sr lrc_tunings[] = {

	{ XE_RTP_NAME("Tuning: Windower HW Filtering"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3599), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, HW_FILTERING))

	  XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN4, HW_FILTERING))

	},



	/* DG2 */

drivers/gpu/drm/xe/xe_wa.c

+2 −2
Original line number Diff line number Diff line
@@ -754,7 +754,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	},

	{ XE_RTP_NAME("22021007897"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))

	  XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))

	},



	/* Xe3_LPG */
@@ -770,7 +770,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	},

	{ XE_RTP_NAME("22021007897"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))

	  XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))

	},

	{ XE_RTP_NAME("14024681466"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),