Unverified Commit a4660bd9 authored by Gustavo Sousa's avatar Gustavo Sousa Committed by Rodrigo Vivi
Browse files

drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN1 



The register COMMON_SLICE_CHICKEN1 is a MCR register on Xe2.
Let's make sure to define a MCR version of it and use it for the
relevant IP versions.

Use XEHP_ as prefix for the register name, since it is MCR as of Xe_HP.

Fixes: a5d22192 ("drm/xe/xe2_hpg: Add set of workarounds")
Fixes: 9f18b55b ("drm/xe/xe2: Add workaround 18033852989")
Bspec: 66534, 71185
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260514-rtp-mcr-check-v3-2-30dd47855fee@intel.com


Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
(cherry picked from commit a672725fdbfc3ea430130039d677c7dc98d59df8)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 16be14ee

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ 
#define   MSAA_OPTIMIZATION_REDUC_DISABLE	REG_BIT(11)



#define COMMON_SLICE_CHICKEN1			XE_REG(0x7010, XE_REG_OPTION_MASKED)

#define XEHP_COMMON_SLICE_CHICKEN1		XE_REG_MCR(0x7010, XE_REG_OPTION_MASKED)

#define   DISABLE_BOTTOM_CLIP_RECTANGLE_TEST	REG_BIT(14)



#define HIZ_CHICKEN					XE_REG(0x7018, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/xe_wa.c

+1 −1
Original line number Diff line number Diff line
@@ -651,7 +651,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	},

	{ XE_RTP_NAME("18033852989"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))

	  XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))

	},

	{ XE_RTP_NAME("15016589081"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),