Unverified Commit 74ba42b2 authored by Clément Léger's avatar Clément Léger Committed by Palmer Dabbelt
Browse files

riscv: hwprobe: export Zhintntl ISA extension 

Export Zihintntl extension[1] through hwprobe.

Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view

 [1]
Signed-off-by: default avatarClément Léger <cleger@rivosinc.com>
Reviewed-by: default avatarEvan Green <evan@rivosinc.com>
Link: https://lore.kernel.org/r/20231114141256.126749-14-cleger@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent eddbfa0d

Documentation/arch/riscv/hwprobe.rst

+3 −0
Original line number Diff line number Diff line
@@ -146,6 +146,9 @@ The following keys are defined: 
  * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is

       supported as defined in the RISC-V ISA manual.



  * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0

       is supported as defined in the RISC-V ISA manual.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

arch/riscv/include/uapi/asm/hwprobe.h

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZVKT		(1 << 26)

#define		RISCV_HWPROBE_EXT_ZFH		(1 << 27)

#define		RISCV_HWPROBE_EXT_ZFHMIN	(1 << 28)

#define		RISCV_HWPROBE_EXT_ZIHINTNTL	(1 << 29)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/sys_riscv.c

+1 −0
Original line number Diff line number Diff line
@@ -173,6 +173,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
		EXT_KEY(ZKSED);

		EXT_KEY(ZKSH);

		EXT_KEY(ZKT);

		EXT_KEY(ZIHINTNTL);



		if (has_vector()) {

			EXT_KEY(ZVBB);