Commit 76a04cd9 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Nuke intel_prepare_shared_dpll() 



intel_prepare_shared_dpll() is now useless, so get rid of it.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-14-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 0bae0872

drivers/gpu/drm/i915/display/intel_display.c

+0 −3
Original line number Diff line number Diff line
@@ -2921,9 +2921,6 @@ static void ilk_crtc_enable(struct intel_atomic_state *state, 
	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);

	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);



	if (new_crtc_state->has_pch_encoder)

		intel_prepare_shared_dpll(new_crtc_state);



	if (intel_crtc_has_dp_encoder(new_crtc_state))

		intel_dp_set_m_n(new_crtc_state, M1_N1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+0 −28
Original line number Diff line number Diff line
@@ -184,34 +184,6 @@ intel_tc_pll_enable_reg(struct drm_i915_private *i915, 
	return MG_PLL_ENABLE(tc_port);

}



/**

 * intel_prepare_shared_dpll - call a dpll's prepare hook

 * @crtc_state: CRTC, and its state, which has a shared dpll

 *

 * This calls the PLL's prepare hook if it has one and if the PLL is not

 * already enabled. The prepare hook is platform specific.

 */

void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct intel_shared_dpll *pll = crtc_state->shared_dpll;



	if (drm_WARN_ON(&dev_priv->drm, pll == NULL))

		return;



	mutex_lock(&dev_priv->dpll.lock);

	drm_WARN_ON(&dev_priv->drm, !pll->state.pipe_mask);

	if (!pll->active_mask) {

		drm_dbg(&dev_priv->drm, "setting up %s\n", pll->info->name);

		drm_WARN_ON(&dev_priv->drm, pll->on);

		assert_shared_dpll_disabled(dev_priv, pll);



		pll->info->funcs->prepare(dev_priv, pll);

	}

	mutex_unlock(&dev_priv->dpll.lock);

}



/**

 * intel_enable_shared_dpll - enable a CRTC's shared DPLL

 * @crtc_state: CRTC, and its state, which has a shared DPLL

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

+0 −11
Original line number Diff line number Diff line
@@ -255,16 +255,6 @@ struct intel_shared_dpll_state { 
 * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs

 */

struct intel_shared_dpll_funcs {

	/**

	 * @prepare:

	 *

	 * Optional hook to perform operations prior to enabling the PLL.

	 * Called from intel_prepare_shared_dpll() function unless the PLL

	 * is already enabled.

	 */

	void (*prepare)(struct drm_i915_private *dev_priv,

			struct intel_shared_dpll *pll);



	/**

	 * @enable:

	 *
@@ -404,7 +394,6 @@ int intel_dpll_get_freq(struct drm_i915_private *i915, 
bool intel_dpll_get_hw_state(struct drm_i915_private *i915,

			     struct intel_shared_dpll *pll,

			     struct intel_dpll_hw_state *hw_state);

void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);

void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);

void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);

void intel_shared_dpll_swap_state(struct intel_atomic_state *state);