Commit 7915d7d5 authored by Jerome Brunet's avatar Jerome Brunet
Browse files

clk: amlogic: gxbb: drop non existing 32k clock parent 



The 32k clock reference a parent 'cts_slow_oscin' with a fixme note saying
that this clock should be provided by AO controller.

The HW probably has this clock but it does not exist at the moment in
any controller implementation. Furthermore, referencing clock by the global
name should be avoided whenever possible.

There is no reason to keep this hack around, at least for now.

Fixes: 14c735c8 ("clk: meson-gxbb: Add EE 32K Clock for CEC")
Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241220-amlogic-clk-gxbb-32k-fixes-v1-2-baca56ecf2db@baylibre.com


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent f38f7fe4

drivers/clk/meson/gxbb.c

+6 −6
Original line number Diff line number Diff line
@@ -1266,14 +1266,13 @@ static struct clk_regmap gxbb_cts_i958 = { 
	},

};



static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {

	{ .fw_name = "xtal", },

/*

	 * FIXME: This clock is provided by the ao clock controller but the

	 * clock is not yet part of the binding of this controller, so string

	 * name must be use to set this parent.

 * This table skips a clock named 'cts_slow_oscin' in the documentation

 * This clock does not exist yet in this controller or the AO one

 */

	{ .name = "cts_slow_oscin", .index = -1 },

static u32 gxbb_32k_clk_parents_val_table[] = { 0, 2, 3 };

static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {

	{ .fw_name = "xtal", },

	{ .hw = &gxbb_fclk_div3.hw },

	{ .hw = &gxbb_fclk_div5.hw },

};
@@ -1283,6 +1282,7 @@ static struct clk_regmap gxbb_32k_clk_sel = { 
		.offset = HHI_32K_CLK_CNTL,

		.mask = 0x3,

		.shift = 16,

		.table = gxbb_32k_clk_parents_val_table,

		},

	.hw.init = &(struct clk_init_data){

		.name = "32k_clk_sel",