Commit 7b9b7651 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2024-08-01' of... 

Merge tag 'drm-intel-fixes-2024-08-01' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-fixes

- Static analysis fix for int overflow
- Fix for HDCP2_STREAM_STATUS macro and removal of PWR_CLK_STATE for gen12

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZqslBkcZlInYdYgm@jlahtine-mobl.ger.corp.intel.com
parents 774c6f27 5b511572

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+3 −3
Original line number Diff line number Diff line
@@ -1658,7 +1658,7 @@ static void skl_wrpll_params_populate(struct skl_wrpll_params *params, 
}



static int

skl_ddi_calculate_wrpll(int clock /* in Hz */,

skl_ddi_calculate_wrpll(int clock,

			int ref_clock,

			struct skl_wrpll_params *wrpll_params)

{
@@ -1683,7 +1683,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */, 
	};

	unsigned int dco, d, i;

	unsigned int p0, p1, p2;

	u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */

	u64 afe_clock = (u64)clock * 1000 * 5; /* AFE Clock is 5x Pixel clock, in Hz */



	for (d = 0; d < ARRAY_SIZE(dividers); d++) {

		for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
@@ -1808,7 +1808,7 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) 
	struct skl_wrpll_params wrpll_params = {};

	int ret;



	ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,

	ret = skl_ddi_calculate_wrpll(crtc_state->port_clock,

				      i915->display.dpll.ref_clks.nssc, &wrpll_params);

	if (ret)

		return ret;

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -251,7 +251,7 @@ 
#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \

					(TRANS_HDCP(dev_priv) ? \

					 TRANS_HDCP2_STREAM_STATUS(trans) : \

					 PIPE_HDCP2_STREAM_STATUS(pipe))

					 PIPE_HDCP2_STREAM_STATUS(port))



#define _PORTA_HDCP2_AUTH_STREAM		0x66F00

#define _PORTB_HDCP2_AUTH_STREAM		0x66F04

drivers/gpu/drm/i915/i915_perf.c

+0 −33
Original line number Diff line number Diff line
@@ -2748,26 +2748,6 @@ oa_configure_all_contexts(struct i915_perf_stream *stream, 
	return 0;

}



static int

gen12_configure_all_contexts(struct i915_perf_stream *stream,

			     const struct i915_oa_config *oa_config,

			     struct i915_active *active)

{

	struct flex regs[] = {

		{

			GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),

			CTX_R_PWR_CLK_STATE,

		},

	};



	if (stream->engine->class != RENDER_CLASS)

		return 0;



	return oa_configure_all_contexts(stream,

					 regs, ARRAY_SIZE(regs),

					 active);

}



static int

lrc_configure_all_contexts(struct i915_perf_stream *stream,

			   const struct i915_oa_config *oa_config,
@@ -2874,7 +2854,6 @@ gen12_enable_metric_set(struct i915_perf_stream *stream, 
{

	struct drm_i915_private *i915 = stream->perf->i915;

	struct intel_uncore *uncore = stream->uncore;

	struct i915_oa_config *oa_config = stream->oa_config;

	bool periodic = stream->periodic;

	u32 period_exponent = stream->period_exponent;

	u32 sqcnt1;
@@ -2918,15 +2897,6 @@ gen12_enable_metric_set(struct i915_perf_stream *stream, 


	intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);



	/*

	 * Update all contexts prior writing the mux configurations as we need

	 * to make sure all slices/subslices are ON before writing to NOA

	 * registers.

	 */

	ret = gen12_configure_all_contexts(stream, oa_config, active);

	if (ret)

		return ret;



	/*

	 * For Gen12, performance counters are context

	 * saved/restored. Only enable it for the context that
@@ -2980,9 +2950,6 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream) 
				   _MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));

	}



	/* Reset all contexts' slices/subslices configurations. */

	gen12_configure_all_contexts(stream, NULL, NULL);



	/* disable the context save/restore or OAR counters */

	if (stream->ctx)

		gen12_configure_oar_context(stream, NULL);