Commit 81a97afe authored by Ciprian Marian Costea's avatar Ciprian Marian Costea Committed by Shawn Guo
Browse files

arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support



Create common part, s32gxxa-evb.dtsi and s32gxxa-rdb.dtsi, for S32G2/S32G3
RDB2\3 and EVB G2/G3 boards to avoid copy duplicate part in boards dts
file. Prepare to add other modules such as FlexCAN, DSPI easily in the
future.

Signed-off-by: default avatarCiprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: default avatarMatthias Brugger <mbrugger@suse.com>
Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent b2194a4c
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/dts-v1/;

#include "s32g2.dtsi"
#include "s32gxxxa-evb.dtsi"

/ {
	model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
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@@ -7,6 +7,7 @@
/dts-v1/;

#include "s32g2.dtsi"
#include "s32gxxxa-rdb.dtsi"

/ {
	model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
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@@ -8,6 +8,7 @@
/dts-v1/;

#include "s32g3.dtsi"
#include "s32gxxxa-rdb.dtsi"

/ {
	model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright 2024 NXP
 *
 * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
 *          Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
 *          Larisa Grigore <larisa.grigore@nxp.com>
 */

&pinctrl {
	i2c0_pins: i2c0-pins {
		i2c0-grp0 {
			pinmux = <0x101>, <0x111>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c0-grp1 {
			pinmux = <0x2352>, <0x2362>;
		};
	};

	i2c0_gpio_pins: i2c0-gpio-pins {
		i2c0-gpio-grp0 {
			pinmux = <0x100>, <0x110>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c0-gpio-grp1 {
			pinmux = <0x2350>, <0x2360>;
		};
	};

	i2c1_pins: i2c1-pins {
		i2c1-grp0 {
			pinmux = <0x131>, <0x141>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c1-grp1 {
			pinmux = <0x2cd2>, <0x2ce2>;
		};
	};

	i2c1_gpio_pins: i2c1-gpio-pins {
		i2c1-gpio-grp0 {
			pinmux = <0x130>, <0x140>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c1-gpio-grp1 {
			pinmux = <0x2cd0>, <0x2ce0>;
		};
	};

	i2c2_pins: i2c2-pins {
		i2c2-grp0 {
			pinmux = <0x151>, <0x161>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c2-grp1 {
			pinmux = <0x2cf2>, <0x2d02>;
		};
	};

	i2c2_gpio_pins: i2c2-gpio-pins {
		i2c2-gpio-grp0 {
			pinmux = <0x150>, <0x160>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c2-gpio-grp1 {
			pinmux = <0x2cf0>, <0x2d00>;
		};
	};

	i2c4_pins: i2c4-pins {
		i2c4-grp0 {
			pinmux = <0x211>, <0x222>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c4-grp1 {
			pinmux = <0x2d43>, <0x2d33>;
		};
	};

	i2c4_gpio_pins: i2c4-gpio-pins {
		i2c4-gpio-grp0 {
			pinmux = <0x210>, <0x220>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c4-gpio-grp1 {
			pinmux = <0x2d40>, <0x2d30>;
		};
	};
};

&i2c0 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-1 = <&i2c0_gpio_pins>;
	status = "okay";
};

&i2c1 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-1 = <&i2c1_gpio_pins>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-1 = <&i2c2_gpio_pins>;
	status = "okay";
};

&i2c4 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&i2c4_pins>;
	pinctrl-1 = <&i2c4_gpio_pins>;
	status = "okay";
};
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright 2024 NXP
 *
 * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
 *          Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
 *          Larisa Grigore <larisa.grigore@nxp.com>
 */

&pinctrl {
	i2c0_pins: i2c0-pins {
		i2c0-grp0 {
			pinmux = <0x1f2>, <0x201>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c0-grp1 {
			pinmux = <0x2353>, <0x2363>;
		};
	};

	i2c0_gpio_pins: i2c0-gpio-pins {
		i2c0-gpio-grp0 {
			pinmux = <0x1f0>, <0x200>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c0-gpio-grp1 {
			pinmux = <0x2350>, <0x2360>;
		};
	};

	i2c2_pins: i2c2-pins {
		i2c2-grp0 {
			pinmux = <0x151>, <0x161>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c2-grp1 {
			pinmux = <0x2cf2>, <0x2d02>;
		};
	};

	i2c2_gpio_pins: i2c2-gpio-pins {
		i2c2-gpio-grp0 {
			pinmux = <0x2cf0>, <0x2d00>;
		};

		i2c2-gpio-grp1 {
			pinmux = <0x150>, <0x160>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};
	};

	i2c4_pins: i2c4-pins {
		i2c4-grp0 {
			pinmux = <0x211>, <0x222>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c4-grp1 {
			pinmux = <0x2d43>, <0x2d33>;
		};
	};

	i2c4_gpio_pins: i2c4-gpio-pins {
		i2c4-gpio-grp0 {
			pinmux = <0x210>, <0x220>;
			drive-open-drain;
			output-enable;
			input-enable;
			slew-rate = <133>;
		};

		i2c4-gpio-grp1 {
			pinmux = <0x2d40>, <0x2d30>;
		};
	};
};

&i2c0 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-1 = <&i2c0_gpio_pins>;
	status = "okay";

	pcal6524: gpio-expander@22 {
		compatible = "nxp,pcal6524";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&i2c2 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-1 = <&i2c2_gpio_pins>;
	status = "okay";
};

&i2c4 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&i2c4_pins>;
	pinctrl-1 = <&i2c4_gpio_pins>;
	status = "okay";
};