Commit 832b63c7 authored by Vladimir Oltean's avatar Vladimir Oltean Committed by Jakub Kicinski
Browse files

net: phy: aquantia: use cached GLOBAL_CFG registers in aqr107_read_rate() 



aqr107_read_rate() - called from aqr107_read_status() even periodically
if there is no PHY IRQ - currently reads GLOBAL_CFG registers to
determine what kind of rate adaptation is in use for the current
phydev->speed. However, GLOBAL_CFG registers are runtime invariants, so
accessing the slow MDIO bus is unnecessary.

Reimplement aqr107_read_rate() by reading from the
priv->global_cfg[i].rade_adapt variables (where i is the entry
corresponding to the current phydev->speed).

Making this change also helps disentangle the code delta between
aqr105_read_rate() and aqr107_read_rate(). They are now identical up to
the code snippet which iterates over priv->global_cfg[]. This will help
eliminate the duplicate code in the upcoming patch.

Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
Link: https://patch.msgid.link/20250821152022.1065237-9-vladimir.oltean@nxp.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 6fa02208

drivers/net/phy/aquantia/aquantia_main.c

+13 −16
Original line number Diff line number Diff line
@@ -568,8 +568,8 @@ static int aqr105_read_status(struct phy_device *phydev) 


static int aqr107_read_rate(struct phy_device *phydev)

{

	u32 config_reg;

	int val;

	struct aqr107_priv *priv = phydev->priv;

	int i, val;



	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);

	if (val < 0)
@@ -583,42 +583,39 @@ static int aqr107_read_rate(struct phy_device *phydev) 
	switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {

	case MDIO_AN_TX_VEND_STATUS1_10BASET:

		phydev->speed = SPEED_10;

		config_reg = VEND1_GLOBAL_CFG_10M;

		break;

	case MDIO_AN_TX_VEND_STATUS1_100BASETX:

		phydev->speed = SPEED_100;

		config_reg = VEND1_GLOBAL_CFG_100M;

		break;

	case MDIO_AN_TX_VEND_STATUS1_1000BASET:

		phydev->speed = SPEED_1000;

		config_reg = VEND1_GLOBAL_CFG_1G;

		break;

	case MDIO_AN_TX_VEND_STATUS1_2500BASET:

		phydev->speed = SPEED_2500;

		config_reg = VEND1_GLOBAL_CFG_2_5G;

		break;

	case MDIO_AN_TX_VEND_STATUS1_5000BASET:

		phydev->speed = SPEED_5000;

		config_reg = VEND1_GLOBAL_CFG_5G;

		break;

	case MDIO_AN_TX_VEND_STATUS1_10GBASET:

		phydev->speed = SPEED_10000;

		config_reg = VEND1_GLOBAL_CFG_10G;

		break;

	default:

		phydev->speed = SPEED_UNKNOWN;

		return 0;

	}



	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);

	if (val < 0)

		return val;

	for (i = 0; i < AQR_NUM_GLOBAL_CFG; i++) {

		struct aqr_global_syscfg *syscfg = &priv->global_cfg[i];



		if (syscfg->speed != phydev->speed)

			continue;



	if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==

	    VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)

		if (syscfg->rate_adapt == AQR_RATE_ADAPT_PAUSE)

			phydev->rate_matching = RATE_MATCH_PAUSE;

		else

			phydev->rate_matching = RATE_MATCH_NONE;

		break;

	}



	return 0;

}