Commit 8a652685 authored by Jerome Brunet's avatar Jerome Brunet
Browse files

clk: amlogic: s4: remove unused data 



Following the removal of the clk_regmap clock table from the s4-peripherals
clock controller driver, it appears some clocks are unused, which means
these are not exported or even registered.

In all likelihood, these clocks have not been tested. Remove the unused
clocks for now. These can added back later when they have been properly
tested.

Reviewed-by: default avatarChuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250623-amlogic-clk-drop-clk-regmap-tables-v4-3-ff04918211cc@baylibre.com


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 4cb53fff

drivers/clk/meson/s4-peripherals.c

+0 −112
Original line number Diff line number Diff line
@@ -3174,118 +3174,6 @@ static struct clk_regmap s4_gen_clk = { 
	},

};



static const struct clk_parent_data s4_adc_extclk_in_parent_data[]  = {

	{ .fw_name = "xtal", },

	{ .fw_name = "fclk_div4", },

	{ .fw_name = "fclk_div3", },

	{ .fw_name = "fclk_div5", },

	{ .fw_name = "fclk_div7", },

	{ .fw_name = "mpll2", },

	{ .fw_name = "gp0_pll", },

	{ .fw_name = "hifi_pll", },

};



static struct clk_regmap s4_adc_extclk_in_mux = {

	.data = &(struct clk_regmap_mux_data) {

		.offset = CLKCTRL_DEMOD_CLK_CTRL,

		.mask = 0x7,

		.shift = 25,

	},

	.hw.init = &(struct clk_init_data){

		.name = "adc_extclk_in_mux",

		.ops = &clk_regmap_mux_ops,

		.parent_data = s4_adc_extclk_in_parent_data,

		.num_parents = ARRAY_SIZE(s4_adc_extclk_in_parent_data),

		.flags = 0,

	},

};



static struct clk_regmap s4_adc_extclk_in_div = {

	.data = &(struct clk_regmap_div_data) {

		.offset = CLKCTRL_DEMOD_CLK_CTRL,

		.shift = 16,

		.width = 7,

	},

	.hw.init = &(struct clk_init_data){

		.name = "adc_extclk_in_div",

		.ops = &clk_regmap_divider_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&s4_adc_extclk_in_mux.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap s4_adc_extclk_in_gate = {

	.data = &(struct clk_regmap_gate_data) {

		.offset = CLKCTRL_DEMOD_CLK_CTRL,

		.bit_idx = 24,

	},

	.hw.init = &(struct clk_init_data){

		.name = "adc_extclk_in",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&s4_adc_extclk_in_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap s4_demod_core_clk_mux = {

	.data = &(struct clk_regmap_mux_data) {

		.offset = CLKCTRL_DEMOD_CLK_CTRL,

		.mask = 0x3,

		.shift = 9,

	},

	.hw.init = &(struct clk_init_data){

		.name = "demod_core_clk_mux",

		.ops = &clk_regmap_mux_ops,

		.parent_data = (const struct clk_parent_data []) {

			{ .fw_name = "xtal", },

			{ .fw_name = "fclk_div7", },

			{ .fw_name = "fclk_div4", },

			{ .hw = &s4_adc_extclk_in_gate.hw }

		},

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap s4_demod_core_clk_div = {

	.data = &(struct clk_regmap_div_data) {

		.offset = CLKCTRL_DEMOD_CLK_CTRL,

		.shift = 0,

		.width = 7,

	},

	.hw.init = &(struct clk_init_data){

		.name = "demod_core_clk_div",

		.ops = &clk_regmap_divider_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&s4_demod_core_clk_mux.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap s4_demod_core_clk_gate = {

	.data = &(struct clk_regmap_gate_data) {

		.offset = CLKCTRL_DEMOD_CLK_CTRL,

		.bit_idx = 8,

	},

	.hw.init = &(struct clk_init_data){

		.name = "demod_core_clk",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&s4_demod_core_clk_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



#define MESON_GATE(_name, _reg, _bit) \

	MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw)