Commit 8beff788 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.10-tag2' of... 

Merge tag 'renesas-clk-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull more Renesas clk driver updates from Geert Uytterhoeven:

 - Miscellaneous fixes and improvements
 - Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on R-Car V4M
 - Add interrupt controller (PLIC) clock and reset on RZ/Five
 - Prepare power domain support for RZ/G2L family members, and add
   actual support on RZ/G3S SoC

* tag 'renesas-clk-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a08g045: Add support for power domains
  clk: renesas: rzg2l: Extend power domain support
  dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S
  dt-bindings: clock: r9a08g045-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g044-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
  clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT
  clk: renesas: r8a7740: Remove unused div4_clk.flags field
  clk: renesas: r9a07g043: Add clock and reset entry for PLIC
  clk: renesas: r8a779h0: Add INTC-EX clock
  clk: renesas: r8a779h0: Add MSIOF clocks
  clk: renesas: r8a779a0: Fix CANFD parent clock
parents 1758c68c 5add5ebc

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+17 −1
Original line number Diff line number Diff line
@@ -57,7 +57,8 @@ properties: 
      can be power-managed through Module Standby should refer to the CPG device

      node in their "power-domains" property, as documented by the generic PM

      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.

    const: 0

      The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could

      be used to reference individual CPG power domains.



  '#reset-cells':

    description:
@@ -76,6 +77,21 @@ required: 


additionalProperties: false



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: renesas,r9a08g045-cpg

    then:

      properties:

        '#power-domain-cells':

          const: 1

    else:

      properties:

        '#power-domain-cells':

          const: 0



examples:

  - |

    cpg: clock-controller@11010000 {

drivers/clk/renesas/clk-r8a73a4.c

+0 −2
Original line number Diff line number Diff line
@@ -30,8 +30,6 @@ struct r8a73a4_cpg { 
#define CPG_PLL2HCR	0xe4

#define CPG_PLL2SCR	0xf4



#define CLK_ENABLE_ON_INIT BIT(0)



struct div4_clk {

	const char *name;

	unsigned int reg;

drivers/clk/renesas/clk-r8a7740.c

+12 −15
Original line number Diff line number Diff line
@@ -26,28 +26,25 @@ struct r8a7740_cpg { 
#define CPG_USBCKCR	0x8c

#define CPG_FRQCRC	0xe0



#define CLK_ENABLE_ON_INIT BIT(0)



struct div4_clk {

	const char *name;

	unsigned int reg;

	unsigned int shift;

	int flags;

};



static struct div4_clk div4_clks[] = {

	{ "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },

	{ "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },

	{ "b", CPG_FRQCRA,  8, CLK_ENABLE_ON_INIT },

	{ "m1", CPG_FRQCRA,  4, CLK_ENABLE_ON_INIT },

	{ "hp", CPG_FRQCRB,  4, 0 },

	{ "hpp", CPG_FRQCRC, 20, 0 },

	{ "usbp", CPG_FRQCRC, 16, 0 },

	{ "s", CPG_FRQCRC, 12, 0 },

	{ "zb", CPG_FRQCRC,  8, 0 },

	{ "m3", CPG_FRQCRC,  4, 0 },

	{ "cp", CPG_FRQCRC,  0, 0 },

	{ NULL, 0, 0, 0 },

	{ "i", CPG_FRQCRA, 20 },

	{ "zg", CPG_FRQCRA, 16 },

	{ "b", CPG_FRQCRA,  8 },

	{ "m1", CPG_FRQCRA,  4 },

	{ "hp", CPG_FRQCRB,  4 },

	{ "hpp", CPG_FRQCRC, 20 },

	{ "usbp", CPG_FRQCRC, 16 },

	{ "s", CPG_FRQCRC, 12 },

	{ "zb", CPG_FRQCRC,  8 },

	{ "m3", CPG_FRQCRC,  4 },

	{ "cp", CPG_FRQCRC,  0 },

	{ NULL, 0, 0 },

};



static const struct clk_div_table div4_div_table[] = {

drivers/clk/renesas/clk-sh73a0.c

+0 −2
Original line number Diff line number Diff line
@@ -34,8 +34,6 @@ struct sh73a0_cpg { 
#define CPG_DSI0PHYCR	0x6c

#define CPG_DSI1PHYCR	0x70



#define CLK_ENABLE_ON_INIT BIT(0)



struct div4_clk {

	const char *name;

	const char *parent;

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -139,7 +139,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 
	DEF_MOD("avb3",		214,	R8A779A0_CLK_S3D2),

	DEF_MOD("avb4",		215,	R8A779A0_CLK_S3D2),

	DEF_MOD("avb5",		216,	R8A779A0_CLK_S3D2),

	DEF_MOD("canfd0",	328,	R8A779A0_CLK_CANFD),

	DEF_MOD("canfd0",	328,	R8A779A0_CLK_S3D2),

	DEF_MOD("csi40",	331,	R8A779A0_CLK_CSI0),

	DEF_MOD("csi41",	400,	R8A779A0_CLK_CSI0),

	DEF_MOD("csi42",	401,	R8A779A0_CLK_CSI0),