Commit 8e96597f authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r9a09g047: Add OPP table

parent 9977754e
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+41 −0
Original line number Diff line number Diff line
@@ -20,6 +20,39 @@ audio_extal_clk: audio-clk {
		clock-frequency = <0>;
	};

	/*
	 * The default cluster table is based on the assumption that the PLLCA55 clock
	 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
	 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
	 * clocked to 1.8GHz as well). The table below should be overridden in the board
	 * DTS based on the PLLCA55 clock frequency.
	 */
	cluster0_opp: opp-table-0 {
		compatible = "operating-points-v2";

		opp-1700000000 {
			opp-hz = /bits/ 64 <1700000000>;
			opp-microvolt = <900000>;
			clock-latency-ns = <300000>;
		};
		opp-850000000 {
			opp-hz = /bits/ 64 <850000000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
		};
		opp-425000000 {
			opp-hz = /bits/ 64 <425000000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
		};
		opp-212500000 {
			opp-hz = /bits/ 64 <212500000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
			opp-suspend;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
@@ -30,6 +63,8 @@ cpu0: cpu@0 {
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu1: cpu@100 {
@@ -38,6 +73,8 @@ cpu1: cpu@100 {
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu2: cpu@200 {
@@ -46,6 +83,8 @@ cpu2: cpu@200 {
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu3: cpu@300 {
@@ -54,6 +93,8 @@ cpu3: cpu@300 {
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
			operating-points-v2 = <&cluster0_opp>;
		};

		L3_CA55: cache-controller-0 {