Commit 917846e9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mailbox-v6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox 

Pull mailbox updates from Jassi Brar:

 - samsung: add gs101-mbox driver

 - microchip: add sbi-ipc driver

 - zynqmp: fix invalid __percpu annotation

 - qcom: add IPQ5424 APCS compatible

 - mpfs fix copy and paste bug

 - th1520: Fix NULL vs IS_ERR() and a memory corruption bug

 - tegra-hsp: clear mailbox before using message

* tag 'mailbox-v6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox:
  riscv: export __cpuid_to_hartid_map
  riscv: sbi: vendorid_list: Add Microchip Technology to the vendor list
  mailbox: th1520: Fix memory corruption due to incorrect array size
  mailbox: zynqmp: Remove invalid __percpu annotation in zynqmp_ipi_probe()
  MAINTAINERS: add entry for Samsung Exynos mailbox driver
  mailbox: add Samsung Exynos driver
  dt-bindings: mailbox: add google,gs101-mbox
  mailbox: qcom: Add support for IPQ5424 APCS IPC
  dt-bindings: mailbox: qcom: Add IPQ5424 APCS compatible
  mailbox: qcom-ipcc: Reset CLEAR_ON_RECV_RD if set from boot firmware
  mailbox: add Microchip IPC support
  dt-bindings: mailbox: add binding for Microchip IPC mailbox controller
  mailbox: tegra-hsp: Clear mailbox before using message
  mailbox: mpfs: fix copy and paste bug in probe
  mailbox: th1520: Fix a NULL vs IS_ERR() bug
parents 9d5db4e3 4783ce32

Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright 2024 Linaro Ltd.

%YAML 1.2

---

$id: http://devicetree.org/schemas/mailbox/google,gs101-mbox.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Samsung Exynos Mailbox Controller



maintainers:

  - Tudor Ambarus <tudor.ambarus@linaro.org>



description:

  The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 flag

  bits for hardware interrupt generation and a shared register for passing

  mailbox messages. When the controller is used by the ACPM interface

  the shared register is ignored and the mailbox controller acts as a doorbell.

  The controller just raises the interrupt to the firmware after the

  ACPM interface has written the message to SRAM.



properties:

  compatible:

    const: google,gs101-mbox



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: pclk



  interrupts:

    description: IRQ line for the RX mailbox.

    maxItems: 1



  '#mbox-cells':

    const: 0



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - interrupts

  - '#mbox-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/google,gs101.h>



    soc {

        #address-cells = <1>;

        #size-cells = <1>;



        ap2apm_mailbox: mailbox@17610000 {

            compatible = "google,gs101-mbox";

            reg = <0x17610000 0x1000>;

            clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>;

            clock-names = "pclk";

            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>;

            #mbox-cells = <0>;

        };

    };

Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip Inter-processor communication (IPC) mailbox controller



maintainers:

  - Valentina Fernandez <valentina.fernandezalanis@microchip.com>



description:

  The Microchip Inter-processor Communication (IPC) facilitates

  message passing between processors using an interrupt signaling

  mechanism.



properties:

  compatible:

    oneOf:

      - description:

          Intended for use by software running in supervisor privileged

          mode (s-mode). This SBI interface is compatible with the Mi-V

          Inter-hart Communication (IHC) IP.

        const: microchip,sbi-ipc



      - description:

          Intended for use by the SBI implementation in machine mode

          (m-mode), this compatible string is for the MIV_IHC Soft-IP.

        const: microchip,miv-ihc-rtl-v2



  reg:

    maxItems: 1



  interrupts:

    minItems: 1

    maxItems: 5



  interrupt-names:

    minItems: 1

    maxItems: 5

    items:

      enum:

        - hart-0

        - hart-1

        - hart-2

        - hart-3

        - hart-4

        - hart-5



  "#mbox-cells":

    description: >

      For "microchip,sbi-ipc", the cell represents the global "logical"

      channel IDs. The meaning of channel IDs are platform firmware dependent.



      For "microchip,miv-ihc-rtl-v2", the cell represents the physical

      channel and does not vary based on the platform firmware.

    const: 1



  microchip,ihc-chan-disabled-mask:

    description: >

      Represents the enable/disable state of the bi-directional IHC

      channels within the MIV-IHC IP configuration.



      A bit set to '1' indicates that the corresponding channel is disabled,

      and any read or write operations to that channel will return zero.



      A bit set to '0' indicates that the corresponding channel is enabled

      and will be accessible through its dedicated address range registers.



      The actual enable/disable state of each channel is determined by the

      IP block’s configuration.

    $ref: /schemas/types.yaml#/definitions/uint16

    maximum: 0x7fff

    default: 0



required:

  - compatible

  - interrupts

  - interrupt-names

  - "#mbox-cells"



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: microchip,sbi-ipc

    then:

      properties:

        reg:

          not: {}

          description:

            The 'microchip,sbi-ipc' operates in a programming model

            that does not require memory-mapped I/O (MMIO) registers

            since it uses SBI ecalls provided by the m-mode/firmware

            SBI implementation to access hardware registers.

        microchip,ihc-chan-disabled-mask: false

    else:

      required:

        - reg

        - microchip,ihc-chan-disabled-mask



additionalProperties: false



examples:

  - |

    mailbox {

      compatible = "microchip,sbi-ipc";

      interrupt-parent = <&plic>;

      interrupts = <180>, <179>, <178>;

      interrupt-names = "hart-1", "hart-2", "hart-3";

      #mbox-cells = <1>;

    };

  - |

    mailbox@50000000 {

      compatible = "microchip,miv-ihc-rtl-v2";

      microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;

      reg = <0x50000000 0x1c000>;

      interrupt-parent = <&plic>;

      interrupts = <180>, <179>, <178>;

      interrupt-names = "hart-1", "hart-2", "hart-3";

      #mbox-cells = <1>;

    };

Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml

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@@ -20,6 +20,7 @@ properties: 
          - enum:

              - qcom,ipq5018-apcs-apps-global

              - qcom,ipq5332-apcs-apps-global

              - qcom,ipq5424-apcs-apps-global

              - qcom,ipq8074-apcs-apps-global

              - qcom,ipq9574-apcs-apps-global

          - const: qcom,ipq6018-apcs-apps-global

MAINTAINERS

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@@ -3064,6 +3064,7 @@ F: drivers/*/*s3c24* 
F:	drivers/*/*s3c64xx*

F:	drivers/*/*s5pv210*

F:	drivers/clocksource/samsung_pwm_timer.c

F:	drivers/mailbox/exynos-mailbox.c

F:	drivers/memory/samsung/

F:	drivers/pwm/pwm-samsung.c

F:	drivers/soc/samsung/
@@ -20826,6 +20827,15 @@ F: arch/arm64/boot/dts/exynos/exynos850* 
F:	drivers/clk/samsung/clk-exynos850.c

F:	include/dt-bindings/clock/exynos850.h









SAMSUNG EXYNOS MAILBOX DRIVER









M:	Tudor Ambarus <tudor.ambarus@linaro.org>









L:	linux-kernel@vger.kernel.org









L:	linux-samsung-soc@vger.kernel.org









S:	Supported









F:	Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml









F:	drivers/mailbox/exynos-mailbox.c









F:	include/linux/mailbox/exynos-message.h

















SAMSUNG EXYNOS PSEUDO RANDOM NUMBER GENERATOR (RNG) DRIVER









M:	Krzysztof Kozlowski <krzk@kernel.org>









L:	linux-crypto@vger.kernel.org

























arch/riscv/include/asm/vendorid_list.h



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−0






























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@@ -6,6 +6,7 @@







#define ASM_VENDOR_LIST_H



















#define ANDES_VENDOR_ID		0x31e









#define MICROCHIP_VENDOR_ID	0x029









#define SIFIVE_VENDOR_ID	0x489









#define THEAD_VENDOR_ID		0x5b7