Commit 91a2cd62 authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/alpm: Add PR_ALPM_CTL register definitions 



Add PR_ALPM_CTL register definition and bits for it.

Bspec: 71014
Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://lore.kernel.org/r/20250526120512.1702815-5-jouni.hogander@intel.com
parent deb8d0fe

drivers/gpu/drm/i915/display/intel_psr_regs.h

+10 −0
Original line number Diff line number Diff line
@@ -266,6 +266,16 @@ 
#define _PIPE_SRCSZ_ERLY_TPT_B	0x71074

#define PIPE_SRCSZ_ERLY_TPT(pipe)	_MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)



#define _PR_ALPM_CTL_A	0x60948

#define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)

#define  PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)

#define  PR_ALPM_CTL_RFB_UPDATE_CONTROL				BIT(5)

#define  PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE	BIT(4)

#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK		REG_GENMASK(1, 0)

#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2	REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0)

#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1)

#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2)



#define _ALPM_CTL_A	0x60950

#define ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)

#define  ALPM_CTL_ALPM_ENABLE				REG_BIT(31)