Commit 922c8928 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a09g047: Add SDHI clocks/resets 



Add SDHI[0-2] clock and reset entries.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarTommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250126134616.37334-3-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 90a2bee8

drivers/clk/renesas/r9a09g047-cpg.c

+31 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ enum clk_ids { 


	/* Internal Core Clocks */

	CLK_PLLCM33_DIV16,

	CLK_PLLCLN_DIV2,

	CLK_PLLCLN_DIV8,

	CLK_PLLCLN_DIV16,

	CLK_PLLDTY_ACPU,

	CLK_PLLDTY_ACPU_DIV4,
@@ -71,6 +73,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { 
	/* Internal Core Clocks */

	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),



	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),

	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),

	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),



	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
@@ -124,6 +128,30 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { 
						BUS_MSTOP(1, BIT(7))),

	DEF_MOD("riic_7_ckm",			CLK_PLLCLN_DIV16, 9, 11, 4, 27,

						BUS_MSTOP(1, BIT(8))),

	DEF_MOD("sdhi_0_imclk",			CLK_PLLCLN_DIV8, 10, 3, 5, 3,

						BUS_MSTOP(8, BIT(2))),

	DEF_MOD("sdhi_0_imclk2",		CLK_PLLCLN_DIV8, 10, 4, 5, 4,

						BUS_MSTOP(8, BIT(2))),

	DEF_MOD("sdhi_0_clk_hs",		CLK_PLLCLN_DIV2, 10, 5, 5, 5,

						BUS_MSTOP(8, BIT(2))),

	DEF_MOD("sdhi_0_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,

						BUS_MSTOP(8, BIT(2))),

	DEF_MOD("sdhi_1_imclk",			CLK_PLLCLN_DIV8, 10, 7, 5, 7,

						BUS_MSTOP(8, BIT(3))),

	DEF_MOD("sdhi_1_imclk2",		CLK_PLLCLN_DIV8, 10, 8, 5, 8,

						BUS_MSTOP(8, BIT(3))),

	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9,

						BUS_MSTOP(8, BIT(3))),

	DEF_MOD("sdhi_1_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,

						BUS_MSTOP(8, BIT(3))),

	DEF_MOD("sdhi_2_imclk",			CLK_PLLCLN_DIV8, 10, 11, 5, 11,

						BUS_MSTOP(8, BIT(4))),

	DEF_MOD("sdhi_2_imclk2",		CLK_PLLCLN_DIV8, 10, 12, 5, 12,

						BUS_MSTOP(8, BIT(4))),

	DEF_MOD("sdhi_2_clk_hs",		CLK_PLLCLN_DIV2, 10, 13, 5, 13,

						BUS_MSTOP(8, BIT(4))),

	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,

						BUS_MSTOP(8, BIT(4))),

};



static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
@@ -143,6 +171,9 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { 
	DEF_RST(9, 14, 4, 15),		/* RIIC_6_MRST */

	DEF_RST(9, 15, 4, 16),		/* RIIC_7_MRST */

	DEF_RST(10, 0, 4, 17),		/* RIIC_8_MRST */

	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */

	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */

	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */

};



const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {