Commit 9483aa44 authored by Shubhrajyoti Datta's avatar Shubhrajyoti Datta Committed by Borislav Petkov (AMD)
Browse files

EDAC/versal: Read num_csrows and num_chans using the correct bitfield macro 

Fix the extraction of num_csrows and num_chans. The extraction of the
num_rows is wrong. Instead of extracting using the FIELD_GET it is
calling FIELD_PREP.

The issue was masked as the default design has the rows as 0.

Fixes: 6f15b178 ("EDAC/versal: Add a Xilinx Versal memory controller driver")
Closes: https://lore.kernel.org/all/60ca157e-6eff-d12c-9dc0-8aeab125edda@linux-m68k.org/


Reported-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: default avatarShubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20231215053352.8740-1-shubhrajyoti.datta@amd.com
parent a39b6ac3

drivers/edac/versal_edac.c

+2 −2
Original line number Diff line number Diff line
@@ -966,10 +966,10 @@ static int mc_probe(struct platform_device *pdev) 
	edac_mc_id = emif_get_id(pdev->dev.of_node);



	regval = readl(ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET);

	num_chans = FIELD_PREP(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval);

	num_chans = FIELD_GET(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval);

	num_chans++;



	num_csrows = FIELD_PREP(XDDR_REG_CONFIG0_NUM_RANKS_MASK, regval);

	num_csrows = FIELD_GET(XDDR_REG_CONFIG0_NUM_RANKS_MASK, regval);

	num_csrows *= 2;

	if (!num_csrows)

		num_csrows = 1;