Commit 949adb47 authored by Bhuvanachandra Pinninti's avatar Bhuvanachandra Pinninti Committed by Alex Deucher
Browse files

drm/amd/display: Migrate DCCG register access from hwseq to dccg component. 



[why]
Direct DCCG register access in hwseq layer was creating register conflicts.

[how]
Migrated DCCG registers from hwseq to dccg component.

Reviewed-by: default avatarMartin Leung <martin.leung@amd.com>
Signed-off-by: default avatarBhuvanachandra Pinninti <bpinnint@amd.com>
Signed-off-by: default avatarWayne Lin <wayne.lin@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 31b15331

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

+53 −1
Original line number Diff line number Diff line
@@ -131,6 +131,54 @@ void dccg2_otg_drop_pixel(struct dccg *dccg, 


void dccg2_init(struct dccg *dccg)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	/* Hardcoded register values for DCN20

	 * These are specific to 100Mhz refclk

	 * Different ASICs with different refclk may override this in their own init

	 */

	REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264);

	REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0);

	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c);



	if (REG(REFCLK_CNTL))

		REG_WRITE(REFCLK_CNTL, 0);

}



void dccg2_refclk_setup(struct dccg *dccg)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	/* REFCLK programming that must occur after hubbub initialization */

	if (REG(REFCLK_CNTL))

		REG_WRITE(REFCLK_CNTL, 0);

}



bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	return REG_READ(MICROSECOND_TIME_BASE_DIV) == 0x00120464;

}



void dccg2_allow_clock_gating(struct dccg *dccg, bool allow)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	if (allow) {

		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);

		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);

	} else {

		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0xFFFFFFFF);

		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF);

	}

}



void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, enable ? 0 : 1);

}



static const struct dccg_funcs dccg2_funcs = {
@@ -139,7 +187,11 @@ static const struct dccg_funcs dccg2_funcs = { 
	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,

	.otg_add_pixel = dccg2_otg_add_pixel,

	.otg_drop_pixel = dccg2_otg_drop_pixel,

	.dccg_init = dccg2_init

	.dccg_init = dccg2_init,

	.refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */

	.allow_clock_gating = dccg2_allow_clock_gating,

	.enable_memory_low_power = dccg2_enable_memory_low_power,

	.is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done

};



struct dccg *dccg2_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

+15 −3
Original line number Diff line number Diff line
@@ -46,7 +46,9 @@ 
	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\

	SR(DCCG_GATE_DISABLE_CNTL),\

	SR(DCCG_GATE_DISABLE_CNTL2)



#define DCCG_SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -81,7 +83,8 @@ 
	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\

	DCCG_SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
@@ -130,7 +133,8 @@ 
	type DISPCLK_CHG_FWD_CORR_DISABLE;\

	type DISPCLK_FREQ_CHANGE_CNTL;\

	type OTG_ADD_PIXEL[MAX_PIPES];\

	type OTG_DROP_PIXEL[MAX_PIPES];

	type OTG_DROP_PIXEL[MAX_PIPES];\

	type DC_MEM_GLOBAL_PWR_REQ_DIS;



#define DCCG3_REG_FIELD_LIST(type) \

	type HDMICHARCLK0_EN;\
@@ -515,6 +519,14 @@ void dccg2_otg_drop_pixel(struct dccg *dccg, 


void dccg2_init(struct dccg *dccg);



void dccg2_refclk_setup(struct dccg *dccg);



bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg);



void dccg2_allow_clock_gating(struct dccg *dccg, bool allow);



void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable);



struct dccg *dccg2_create(

	struct dc_context *ctx,

	const struct dccg_registers *regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

+2 −3
Original line number Diff line number Diff line
@@ -1885,9 +1885,8 @@ void dcn10_init_hw(struct dc *dc) 


	if (!dc->debug.disable_clock_gate) {

		/* enable all DCN clock gating */

		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);



		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);

		if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

			dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);



		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

	}

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

+8 −21
Original line number Diff line number Diff line
@@ -357,26 +357,10 @@ void dcn20_enable_power_gating_plane( 


void dcn20_dccg_init(struct dce_hwseq *hws)

{

	/*

	 * set MICROSECOND_TIME_BASE_DIV

	 * 100Mhz refclk -> 0x120264

	 * 27Mhz refclk -> 0x12021b

	 * 48Mhz refclk -> 0x120230

	 *

	 */

	REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);

	struct dc *dc = hws->ctx->dc;



	/*

	 * set MILLISECOND_TIME_BASE_DIV

	 * 100Mhz refclk -> 0x1186a0

	 * 27Mhz refclk -> 0x106978

	 * 48Mhz refclk -> 0x10bb80

	 *

	 */

	REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);



	/* This value is dependent on the hardware pipeline delay so set once per SOC */

	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);

	if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init)

		dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg);

}



void dcn20_disable_vga(
@@ -3155,8 +3139,11 @@ void dcn20_fpga_init_hw(struct dc *dc) 
	REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);



	dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2);

	if (REG(REFCLK_CNTL))

		REG_WRITE(REFCLK_CNTL, 0);



	hws->funcs.dccg_init(hws);



	if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup)

		dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg);

	//

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

+2 −3
Original line number Diff line number Diff line
@@ -364,9 +364,8 @@ void dcn201_init_hw(struct dc *dc) 


	if (!dc->debug.disable_clock_gate) {

		/* enable all DCN clock gating */

		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);



		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);

		if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

			dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);



		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

	}