Commit 96557f78 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd: GFX12 changes for converting tiling flags to modifiers 



GFX12 swizzle mode and GCC formats changed and is much simpler. Use a
seperate function for the same. Changes:

* Swizzle mode is now 3 bits only
* DCC enablement doesn't come from tiling_flags, it is always set in modifiers
* DCC max compressed block size of 128B

Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: default avatarRodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7d09d80b

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+37 −0
Original line number Diff line number Diff line
@@ -718,6 +718,37 @@ extract_render_dcc_offset(struct amdgpu_device *adev, 
	return 0;

}



static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb)

{

	struct amdgpu_device *adev = drm_to_adev(afb->base.dev);

	const struct drm_format_info *format_info;

	u64 modifier = 0;

	int tile = 0;

	int swizzle = 0;



	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {

		tile = AMD_FMT_MOD_TILE_VER_GFX12;

		swizzle =  AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE);

	}



	modifier =

		AMD_FMT_MOD |

		AMD_FMT_MOD_SET(TILE, swizzle) |

		AMD_FMT_MOD_SET(TILE_VERSION,  tile) |

		AMD_FMT_MOD_SET(DCC, 0) |

		AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, 0);



	format_info = amdgpu_lookup_format_info(afb->base.format->format,

						modifier);

	if (!format_info)

		return -EINVAL;



	afb->base.modifier = modifier;

	afb->base.flags |= DRM_MODE_FB_MODIFIERS;



	return 0;

}



static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)

{

	struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
@@ -742,6 +773,12 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) 
		int pipes = ilog2(num_pipes);

		uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);





		if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {

			convert_tiling_flags_to_modifier_gfx12(afb);

			return 0;

		}



		switch (swizzle >> 2) {

		case 0: /* 256B */

			block_size_bits = 8;

include/uapi/drm/drm_fourcc.h

+3 −0
Original line number Diff line number Diff line
@@ -1540,6 +1540,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) 
#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18

#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3



#define AMD_FMT_MOD_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT     3

#define AMD_FMT_MOD_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK      0x3 /* 0:64B, 1:128B, 2:256B */



/*

 * DCC supports embedding some clear colors directly in the DCC surface.

 * However, on older GPUs the rendering HW ignores the embedded clear color