Commit 982a847c authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/poe' into for-next/core 

* for-next/poe: (31 commits)
  arm64: pkeys: remove redundant WARN
  kselftest/arm64: Add test case for POR_EL0 signal frame records
  kselftest/arm64: parse POE_MAGIC in a signal frame
  kselftest/arm64: add HWCAP test for FEAT_S1POE
  selftests: mm: make protection_keys test work on arm64
  selftests: mm: move fpregs printing
  kselftest/arm64: move get_header()
  arm64: add Permission Overlay Extension Kconfig
  arm64: enable PKEY support for CPUs with S1POE
  arm64: enable POE and PIE to coexist
  arm64/ptrace: add support for FEAT_POE
  arm64: add POE signal support
  arm64: implement PKEYS support
  arm64: add pte_access_permitted_no_overlay()
  arm64: handle PKEY/POE faults
  arm64: mask out POIndex when modifying a PTE
  arm64: convert protection key into vm_flags and pgprot values
  arm64: add POIndex defines
  arm64: re-order MTE VM_ flags
  arm64: enable the Permission Overlay Extension for EL0
  ...
parents 3175e051 10166c23

Documentation/arch/arm64/elf_hwcaps.rst

+2 −0
Original line number Diff line number Diff line
@@ -365,6 +365,8 @@ HWCAP2_SME_SF8DP2 
HWCAP2_SME_SF8DP4

    Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.



HWCAP2_POE

    Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001.



4. Unused AT_HWCAP bits

-----------------------

arch/arm64/Kconfig

+23 −0
Original line number Diff line number Diff line
@@ -2138,6 +2138,29 @@ config ARM64_EPAN 
	  if the cpu does not implement the feature.

endmenu # "ARMv8.7 architectural features"



menu "ARMv8.9 architectural features"



config ARM64_POE

	prompt "Permission Overlay Extension"

	def_bool y

	select ARCH_USES_HIGH_VMA_FLAGS

	select ARCH_HAS_PKEYS

	help

	  The Permission Overlay Extension is used to implement Memory

	  Protection Keys. Memory Protection Keys provides a mechanism for

	  enforcing page-based protections, but without requiring modification

	  of the page tables when an application changes protection domains.



	  For details, see Documentation/core-api/protection-keys.rst



	  If unsure, say y.



config ARCH_PKEY_BITS

	int

	default 3



endmenu # "ARMv8.9 architectural features"



config ARM64_SVE

	bool "ARM Scalable Vector Extension support"

	default y

arch/arm64/include/asm/cpufeature.h

+6 −0
Original line number Diff line number Diff line
@@ -832,6 +832,12 @@ static inline bool system_supports_lpa2(void) 
	return cpus_have_final_cap(ARM64_HAS_LPA2);

}



static inline bool system_supports_poe(void)

{

	return IS_ENABLED(CONFIG_ARM64_POE) &&

		alternative_has_cap_unlikely(ARM64_HAS_S1POE);

}



int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);

bool try_emulate_mrs(struct pt_regs *regs, u32 isn);

arch/arm64/include/asm/el2_setup.h

+8 −0
Original line number Diff line number Diff line
@@ -192,6 +192,14 @@ 
	orr	x0, x0, #HFGxTR_EL2_nPIRE0_EL1



.Lskip_pie_fgt_\@:

	mrs_s	x1, SYS_ID_AA64MMFR3_EL1

	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4

	cbz	x1, .Lskip_poe_fgt_\@



	/* Disable trapping of POR_EL0 */

	orr	x0, x0, #HFGxTR_EL2_nPOR_EL0



.Lskip_poe_fgt_\@:

	msr_s	SYS_HFGRTR_EL2, x0

	msr_s	SYS_HFGWTR_EL2, x0

	msr_s	SYS_HFGITR_EL2, xzr

arch/arm64/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -157,6 +157,7 @@ 
#define KERNEL_HWCAP_SME_SF8FMA		__khwcap2_feature(SME_SF8FMA)

#define KERNEL_HWCAP_SME_SF8DP4		__khwcap2_feature(SME_SF8DP4)

#define KERNEL_HWCAP_SME_SF8DP2		__khwcap2_feature(SME_SF8DP2)

#define KERNEL_HWCAP_POE		__khwcap2_feature(POE)



/*

 * This yields a mask that user programs can use to figure out what