Commit 98dbe56a authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: Handle TSB CSYNC traps 



The architecture introduces a trap for TSB CSYNC that fits in
the same EC as LS64 and PSB CSYNC. Let's deal with it in a similar
way.

It's not that we expect this to be useful any time soon anyway.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent af2d78dc

arch/arm64/include/asm/esr.h

+2 −1
Original line number Diff line number Diff line
@@ -182,10 +182,11 @@ 
#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)

#define ESR_ELx_xVC_IMM_MASK	((UL(1) << 16) - 1)



/* ISS definitions for LD64B/ST64B/PSBCSYNC instructions */

/* ISS definitions for LD64B/ST64B/{T,P}SBCSYNC instructions */

#define ESR_ELx_ISS_OTHER_ST64BV	(0)

#define ESR_ELx_ISS_OTHER_ST64BV0	(1)

#define ESR_ELx_ISS_OTHER_LDST64B	(2)

#define ESR_ELx_ISS_OTHER_TSBCSYNC	(3)

#define ESR_ELx_ISS_OTHER_PSBCSYNC	(4)



#define DISR_EL1_IDS		(UL(1) << 24)

arch/arm64/kvm/emulate-nested.c

+1 −0
Original line number Diff line number Diff line
@@ -2044,6 +2044,7 @@ static const union trap_config non_0x18_fgt[] __initconst = { 
	FGT(HFGITR, SVC_EL1, 1),

	FGT(HFGITR, SVC_EL0, 1),

	FGT(HFGITR, ERET, 1),

	FGT(HFGITR2, TSBCSYNC, 1),

};



static union trap_config get_trap_config(u32 sysreg)

arch/arm64/kvm/handle_exit.c

+5 −0
Original line number Diff line number Diff line
@@ -347,6 +347,11 @@ static int handle_other(struct kvm_vcpu *vcpu) 
		if (is_l2)

			fwd = !(hcrx & HCRX_EL2_EnALS);

		break;

	case ESR_ELx_ISS_OTHER_TSBCSYNC:

		allowed = kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceBuffer, TRBE_V1P1);

		if (is_l2)

			fwd = (__vcpu_sys_reg(vcpu, HFGITR2_EL2) & HFGITR2_EL2_TSBCSYNC);

		break;

	case ESR_ELx_ISS_OTHER_PSBCSYNC:

		allowed = kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, V1P5);

		if (is_l2)