Commit 9ad55a67 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull soundwire updates from Vinod Koul:

 - structure optimization of few bus structures and header updates

 - support for 2.0 disco spec

 - amd driver updates for acp revision, refactoring code and support for
   acp6.3

 - soft reset support for cadence driver

* tag 'soundwire-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire: (24 commits)
  soundwire: Minor formatting fixups in sdw.h header
  soundwire: Update the includes on the sdw.h header
  soundwire: cadence: clear MCP BLOCK_WAKEUP in init
  soundwire: cadence: add soft-reset on startup
  soundwire: intel_auxdevice: add kernel parameter for mclk divider
  soundwire: mipi-disco: add support for DP0/DPn 'lane-list' property
  soundwire: mipi-disco: add new properties from 2.0 spec
  soundwire: mipi-disco: add comment on DP0-supported property
  soundwire: mipi-disco: add support for peripheral channelprepare timeout
  soundwire: mipi_disco: add support for clock-scales property
  soundwire: mipi-disco: add error handling for property array read
  soundwire: mipi-disco: remove DPn audio-modes
  soundwire: optimize sdw_dpn_prop
  soundwire: optimize sdw_dp0_prop
  soundwire: optimize sdw_slave_prop
  soundwire: optimize sdw_bus structure
  soundwire: optimize sdw_master_prop
  soundwire: optimize sdw_stream_runtime memory layout
  soundwire: mipi_disco: add MIPI-specific property_read_bool() helpers
  soundwire: Correct some typos in comments
  ...
parents 0ce9a5ff dd690b31
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+1 −0
Original line number Diff line number Diff line
@@ -174,6 +174,7 @@ is applicable::
	SCSI	Appropriate SCSI support is enabled.
			A lot of drivers have their options described inside
			the Documentation/scsi/ sub-directory.
        SDW     SoundWire support is enabled.
	SECURITY Different security models are enabled.
	SELINUX SELinux support is enabled.
	SERIAL	Serial support is enabled.
+4 −0
Original line number Diff line number Diff line
@@ -6075,6 +6075,10 @@
			non-zero "wait" parameter.  See weight_single
			and weight_many.

	sdw_mclk_divider=[SDW]
			Specify the MCLK divider for Intel SoundWire buses in
			case the BIOS does not provide the clock rate properly.

	skew_tick=	[KNL,EARLY] Offset the periodic timer tick per cpu to mitigate
			xtime_lock contention on larger systems, and/or RCU lock
			contention on all systems with CONFIG_MAXSMP set.
+1 −0
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ static struct sdw_amd_ctx *sdw_amd_probe_controller(struct sdw_amd_res *res)

		sdw_pdata[index].instance = index;
		sdw_pdata[index].acp_sdw_lock = res->acp_lock;
		sdw_pdata[index].acp_rev = res->acp_rev;
		pdevinfo[index].name = "amd_sdw_manager";
		pdevinfo[index].id = index;
		pdevinfo[index].parent = res->parent;
+64 −35
Original line number Diff line number Diff line
@@ -433,12 +433,18 @@ static int amd_sdw_port_params(struct sdw_bus *bus, struct sdw_port_params *p_pa
	u32 frame_fmt_reg, dpn_frame_fmt;

	dev_dbg(amd_manager->dev, "p_params->num:0x%x\n", p_params->num);
	switch (amd_manager->acp_rev) {
	case ACP63_PCI_REV_ID:
		switch (amd_manager->instance) {
		case ACP_SDW0:
		frame_fmt_reg = sdw0_manager_dp_reg[p_params->num].frame_fmt_reg;
			frame_fmt_reg = acp63_sdw0_dp_reg[p_params->num].frame_fmt_reg;
			break;
		case ACP_SDW1:
		frame_fmt_reg = sdw1_manager_dp_reg[p_params->num].frame_fmt_reg;
			frame_fmt_reg = acp63_sdw1_dp_reg[p_params->num].frame_fmt_reg;
			break;
		default:
			return -EINVAL;
		}
		break;
	default:
		return -EINVAL;
@@ -465,20 +471,28 @@ static int amd_sdw_transport_params(struct sdw_bus *bus,
	u32 frame_fmt_reg, sample_int_reg, hctrl_dp0_reg;
	u32 offset_reg, lane_ctrl_ch_en_reg;

	switch (amd_manager->acp_rev) {
	case ACP63_PCI_REV_ID:
		switch (amd_manager->instance) {
		case ACP_SDW0:
		frame_fmt_reg = sdw0_manager_dp_reg[params->port_num].frame_fmt_reg;
		sample_int_reg = sdw0_manager_dp_reg[params->port_num].sample_int_reg;
		hctrl_dp0_reg = sdw0_manager_dp_reg[params->port_num].hctrl_dp0_reg;
		offset_reg = sdw0_manager_dp_reg[params->port_num].offset_reg;
		lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
			frame_fmt_reg = acp63_sdw0_dp_reg[params->port_num].frame_fmt_reg;
			sample_int_reg = acp63_sdw0_dp_reg[params->port_num].sample_int_reg;
			hctrl_dp0_reg = acp63_sdw0_dp_reg[params->port_num].hctrl_dp0_reg;
			offset_reg = acp63_sdw0_dp_reg[params->port_num].offset_reg;
			lane_ctrl_ch_en_reg =
					acp63_sdw0_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
			break;
		case ACP_SDW1:
		frame_fmt_reg = sdw1_manager_dp_reg[params->port_num].frame_fmt_reg;
		sample_int_reg = sdw1_manager_dp_reg[params->port_num].sample_int_reg;
		hctrl_dp0_reg = sdw1_manager_dp_reg[params->port_num].hctrl_dp0_reg;
		offset_reg = sdw1_manager_dp_reg[params->port_num].offset_reg;
		lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
			frame_fmt_reg = acp63_sdw1_dp_reg[params->port_num].frame_fmt_reg;
			sample_int_reg = acp63_sdw1_dp_reg[params->port_num].sample_int_reg;
			hctrl_dp0_reg = acp63_sdw1_dp_reg[params->port_num].hctrl_dp0_reg;
			offset_reg = acp63_sdw1_dp_reg[params->port_num].offset_reg;
			lane_ctrl_ch_en_reg =
					acp63_sdw1_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
			break;
		default:
			return -EINVAL;
		}
		break;
	default:
		return -EINVAL;
@@ -520,12 +534,20 @@ static int amd_sdw_port_enable(struct sdw_bus *bus,
	u32 dpn_ch_enable;
	u32 lane_ctrl_ch_en_reg;

	switch (amd_manager->acp_rev) {
	case ACP63_PCI_REV_ID:
		switch (amd_manager->instance) {
		case ACP_SDW0:
		lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;
			lane_ctrl_ch_en_reg =
					acp63_sdw0_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;
			break;
		case ACP_SDW1:
		lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;
			lane_ctrl_ch_en_reg =
					acp63_sdw1_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;
			break;
		default:
			return -EINVAL;
		}
		break;
	default:
		return -EINVAL;
@@ -910,6 +932,7 @@ static int amd_sdw_manager_probe(struct platform_device *pdev)
	amd_manager->mmio = amd_manager->acp_mmio +
			    (amd_manager->instance * SDW_MANAGER_REG_OFFSET);
	amd_manager->acp_sdw_lock = pdata->acp_sdw_lock;
	amd_manager->acp_rev = pdata->acp_rev;
	amd_manager->cols_index = sdw_find_col_index(AMD_SDW_DEFAULT_COLUMNS);
	amd_manager->rows_index = sdw_find_row_index(AMD_SDW_DEFAULT_ROWS);
	amd_manager->dev = dev;
@@ -926,15 +949,21 @@ static int amd_sdw_manager_probe(struct platform_device *pdev)
	 * information.
	 */
	amd_manager->bus.controller_id = 0;

	dev_dbg(dev, "acp_rev:0x%x\n", amd_manager->acp_rev);
	switch (amd_manager->acp_rev) {
	case ACP63_PCI_REV_ID:
		switch (amd_manager->instance) {
		case ACP_SDW0:
		amd_manager->num_dout_ports = AMD_SDW0_MAX_TX_PORTS;
		amd_manager->num_din_ports = AMD_SDW0_MAX_RX_PORTS;
			amd_manager->num_dout_ports = AMD_ACP63_SDW0_MAX_TX_PORTS;
			amd_manager->num_din_ports = AMD_ACP63_SDW0_MAX_RX_PORTS;
			break;
		case ACP_SDW1:
		amd_manager->num_dout_ports = AMD_SDW1_MAX_TX_PORTS;
		amd_manager->num_din_ports = AMD_SDW1_MAX_RX_PORTS;
			amd_manager->num_dout_ports = AMD_ACP63_SDW1_MAX_TX_PORTS;
			amd_manager->num_din_ports = AMD_ACP63_SDW1_MAX_RX_PORTS;
			break;
		default:
			return -EINVAL;
		}
		break;
	default:
		return -EINVAL;
+8 −8
Original line number Diff line number Diff line
@@ -155,12 +155,12 @@
#define AMD_SDW_IRQ_MASK_8TO11		0x000c7777
#define AMD_SDW_IRQ_ERROR_MASK		0xff
#define AMD_SDW_MAX_FREQ_NUM		1
#define AMD_SDW0_MAX_TX_PORTS		3
#define AMD_SDW0_MAX_RX_PORTS		3
#define AMD_SDW1_MAX_TX_PORTS		1
#define AMD_SDW1_MAX_RX_PORTS		1
#define AMD_SDW0_MAX_DAI		6
#define AMD_SDW1_MAX_DAI		2
#define AMD_ACP63_SDW0_MAX_TX_PORTS		3
#define AMD_ACP63_SDW0_MAX_RX_PORTS		3
#define AMD_ACP63_SDW1_MAX_TX_PORTS		1
#define AMD_ACP63_SDW1_MAX_RX_PORTS		1
#define AMD_ACP63_SDW0_MAX_DAI		6
#define AMD_ACP63_SDW1_MAX_DAI		2
#define AMD_SDW_SLAVE_0_ATTACHED	5
#define AMD_SDW_SSP_COUNTER_VAL		3

@@ -222,7 +222,7 @@ struct sdw_manager_dp_reg {
 * in SoundWire DMA driver.
 */

static struct sdw_manager_dp_reg sdw0_manager_dp_reg[AMD_SDW0_MAX_DAI] =  {
static struct sdw_manager_dp_reg acp63_sdw0_dp_reg[AMD_ACP63_SDW0_MAX_DAI] =  {
	{ACP_SW_AUDIO0_TX_FRAME_FORMAT, ACP_SW_AUDIO0_TX_SAMPLEINTERVAL, ACP_SW_AUDIO0_TX_HCTRL_DP0,
	 ACP_SW_AUDIO0_TX_OFFSET_DP0, ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP0},
	{ACP_SW_AUDIO1_TX_FRAME_FORMAT, ACP_SW_AUDIO1_TX_SAMPLEINTERVAL, ACP_SW_AUDIO1_TX_HCTRL,
@@ -237,7 +237,7 @@ static struct sdw_manager_dp_reg sdw0_manager_dp_reg[AMD_SDW0_MAX_DAI] = {
	 ACP_SW_AUDIO2_RX_OFFSET, ACP_SW_AUDIO2_RX_CHANNEL_ENABLE_DP0},
};

static struct sdw_manager_dp_reg sdw1_manager_dp_reg[AMD_SDW1_MAX_DAI] =  {
static struct sdw_manager_dp_reg acp63_sdw1_dp_reg[AMD_ACP63_SDW1_MAX_DAI] =  {
	{ACP_SW_AUDIO1_TX_FRAME_FORMAT, ACP_SW_AUDIO1_TX_SAMPLEINTERVAL, ACP_SW_AUDIO1_TX_HCTRL,
	 ACP_SW_AUDIO1_TX_OFFSET, ACP_SW_AUDIO1_TX_CHANNEL_ENABLE_DP0},
	{ACP_SW_AUDIO1_RX_FRAME_FORMAT, ACP_SW_AUDIO1_RX_SAMPLEINTERVAL, ACP_SW_AUDIO1_RX_HCTRL,
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