Commit 9ffa0e70 authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Bjorn Helgaas
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PCI: keystone: Don't enable BAR 0 for AM654x 

After 6ab15b5e ("PCI: dwc: keystone: Convert .scan_bus() callback to
use add_bus"), ks_pcie_v3_65_add_bus() enabled BAR 0 for both v3.65a and
v4.90a devices.  On the AM654x SoC, which uses v4.90a, enabling BAR 0
causes Completion Timeouts when setting up MSI-X.  These timeouts delay
boot of the AM654x by about 45 seconds.

Move the BAR 0 initialization to ks_pcie_msi_host_init(), which is only
used for v3.65a devices, and remove ks_pcie_v3_65_add_bus().

[bhelgaas: commit log]
Fixes: 6ab15b5e ("PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus")
Link: https://lore.kernel.org/linux-pci/20240328085041.2916899-3-s-vadapalli@ti.com


Suggested-by: default avatarBjorn Helgaas <helgaas@kernel.org>
Suggested-by: default avatarNiklas Cassel <cassel@kernel.org>
Suggested-by: default avatarSerge Semin <fancer.lancer@gmail.com>
Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarNiklas Cassel <cassel@kernel.org>
parent 5125fdc3

drivers/pci/controller/dwc/pci-keystone.c

+18 −34
Original line number Diff line number Diff line
@@ -289,6 +289,24 @@ static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) 


static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);



	/* Configure and set up BAR0 */

	ks_pcie_set_dbi_mode(ks_pcie);



	/* Enable BAR0 */

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);



	ks_pcie_clear_dbi_mode(ks_pcie);



	/*

	 * For BAR0, just setting bus address for inbound writes (MSI) should

	 * be sufficient.  Use physical address to avoid any conflicts.

	 */

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);



	pp->msi_irq_chip = &ks_pcie_msi_irq_chip;

	return dw_pcie_allocate_domains(pp);

}
@@ -445,44 +463,10 @@ static struct pci_ops ks_child_pcie_ops = { 
	.write = pci_generic_config_write,

};



/**

 * ks_pcie_v3_65_add_bus() - keystone add_bus post initialization

 * @bus: A pointer to the PCI bus structure.

 *

 * This sets BAR0 to enable inbound access for MSI_IRQ register

 */

static int ks_pcie_v3_65_add_bus(struct pci_bus *bus)

{

	struct dw_pcie_rp *pp = bus->sysdata;

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);



	if (!pci_is_root_bus(bus))

		return 0;



	/* Configure and set up BAR0 */

	ks_pcie_set_dbi_mode(ks_pcie);



	/* Enable BAR0 */

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);



	ks_pcie_clear_dbi_mode(ks_pcie);



	 /*

	  * For BAR0, just setting bus address for inbound writes (MSI) should

	  * be sufficient.  Use physical address to avoid any conflicts.

	  */

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);



	return 0;

}



static struct pci_ops ks_pcie_ops = {

	.map_bus = dw_pcie_own_conf_map_bus,

	.read = pci_generic_config_read,

	.write = pci_generic_config_write,

	.add_bus = ks_pcie_v3_65_add_bus,

};



/**