Commit a036db39 authored by Ray Wu's avatar Ray Wu Committed by Alex Deucher
Browse files

drm/amd/display: disable replay when crc source is enabled 



[Why]
IGT CRC tests fail on replay panels due to invalid CRC values
captured when replay is active.

[How]
- Disable replay when CRC source is enabled; set flag to
  prevent unexpected re-enable
- Reset flag when CRC source is disabled to allow replay

Reviewed-by: default avatarChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarRay Wu <ray.wu@amd.com>
Signed-off-by: default avatarMatthew Stewart <matthew.stewart2@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cdd9b2d7

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

+1 −0
Original line number Diff line number Diff line
@@ -815,6 +815,7 @@ struct amdgpu_dm_connector { 


	int sr_skip_count;

	bool disallow_edp_enter_psr;

	bool disallow_edp_enter_replay;



	/* Record progress status of mst*/

	uint8_t mst_status;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

+22 −3
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#include "dc.h"

#include "amdgpu_securedisplay.h"

#include "amdgpu_dm_psr.h"

#include "amdgpu_dm_replay.h"



static const char *const pipe_crc_sources[] = {

	"none",
@@ -502,6 +503,7 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 
{

	struct amdgpu_device *adev = drm_to_adev(crtc->dev);

	struct dc_stream_state *stream_state = dm_crtc_state->stream;

	struct amdgpu_dm_connector *aconnector = NULL;

	bool enable = amdgpu_dm_is_valid_crc_source(source);

	int ret = 0;
@@ -509,12 +511,23 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 
	if (!stream_state)

		return -EINVAL;



	/* Get connector from stream */

	aconnector = (struct amdgpu_dm_connector *)stream_state->dm_stream_context;



	mutex_lock(&adev->dm.dc_lock);





	if (enable) {

		/* For PSR1, check that the panel has exited PSR */

		if (stream_state->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)

			amdgpu_dm_psr_wait_disable(stream_state);



		/* Set flag to disallow enter replay when CRC source is enabled */

		if (aconnector)

			aconnector->disallow_edp_enter_replay = true;

		amdgpu_dm_replay_disable(stream_state);

	}



	/* Enable or disable CRTC CRC generation */

	if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {

		if (!dc_stream_configure_crc(stream_state->ctx->dc,
@@ -536,6 +549,12 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 
					    DYN_EXPANSION_AUTO);

	}



	if (!enable) {

		/* Clear flag to allow enter replay when CRC source is disabled */

		if (aconnector)

			aconnector->disallow_edp_enter_replay = false;

	}



unlock:

	mutex_unlock(&adev->dm.dc_lock);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

+7 −0
Original line number Diff line number Diff line
@@ -154,10 +154,17 @@ bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait) 
{

	bool replay_active = true;

	struct dc_link *link = NULL;

	struct amdgpu_dm_connector *aconnector = NULL;



	if (stream == NULL)

		return false;



	/* Check if replay is disabled by connector flag */

	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;

	if (!aconnector || aconnector->disallow_edp_enter_replay) {

		return false;

	}



	link = stream->link;



	if (link) {